Subversion Repositories freemyipod

//

#include "global.h"

//

#include "synopsysotg.h"

//    Copyright 2010 TheSeven

#include "usb.h"

//

#include "timer.h"

//

#include "util.h"

//    This file is part of emCORE.

//

#ifndef SYNOPSYSOTG_AHB_BURST_LEN

//    emCORE is free software: you can redistribute it and/or

#define SYNOPSYSOTG_AHB_BURST_LEN 5

//    modify it under the terms of the GNU General Public License as

#endif

//    published by the Free Software Foundation, either version 2 of the

#ifndef SYNOPSYSOTG_AHB_THRESHOLD

//    License, or (at your option) any later version.

#define SYNOPSYSOTG_AHB_THRESHOLD 8

//

#endif

//    emCORE is distributed in the hope that it will be useful,

#ifndef SYNOPSYSOTG_TURNAROUND

//    but WITHOUT ANY WARRANTY; without even the implied warranty of

#define SYNOPSYSOTG_TURNAROUND 3

//    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

#endif

//    See the GNU General Public License for more details.

//

static void synopsysotg_flush_out_endpoint(const struct usb_instance* instance, int ep)

//    You should have received a copy of the GNU General Public License along

{

//    with emCORE.  If not, see <http://www.gnu.org/licenses/>.

    const struct synopsysotg_config* data = (const struct synopsysotg_config*)instance->driver_config;

//

    if (data->core->outep_regs[ep].doepctl.b.epena)

//

    {

        // We are waiting for an OUT packet on this endpoint, which might arrive any moment.

        // Assert a global output NAK to avoid race conditions while shutting down the endpoint.

#include "global.h"

        synopsysotg_target_disable_irq(instance);

#include "mmu.h"

        data->core->dregs.dctl.b.sgoutnak = 1;

#include "panic.h"

        while (!(data->core->gregs.gintsts.b.goutnakeff));

#include "usbdrv.h"

        union synopsysotg_depctl doepctl = { .b = { .snak = 1, .epdis = 1 } };

#include "thread.h"

        data->core->outep_regs[ep].doepctl = doepctl;

#include "timer.h"

        while (!(data->core->outep_regs[ep].doepint.b.epdisabled));

#include "usb.h"

        data->core->dregs.dctl.b.cgoutnak = 1;

#include "usb_ch9.h"

        synopsysotg_target_enable_irq(instance);

#include "synopsysotg.h"

    }

#include "util.h"

    data->core->outep_regs[ep].doepctl.b.usbactep = 0;

#include "interrupt.h"

    // Reset the transfer size register. Not strictly necessary, but can't hurt.

#include "clockgates.h"

    data->core->outep_regs[ep].doeptsiz.d32 = 0;

#include "power.h"

}

static void synopsysotg_flush_in_endpoint(const struct usb_instance* instance, int ep)

struct ep_type

{

{

    const struct synopsysotg_config* data = (const struct synopsysotg_config*)instance->driver_config;

    bool active;

    if (data->core->inep_regs[ep].diepctl.b.epena)

    bool busy;

    {

    bool done;

        // We are shutting down an endpoint that might still have IN packets in the FIFO.

    int rc;

        // Disable the endpoint, wait for things to settle, and flush the relevant FIFO.

    int size;

        synopsysotg_target_disable_irq(instance);

    struct wakeup complete;

        data->core->inep_regs[ep].diepctl.b.snak = 1;

} ;

        while (!(data->core->inep_regs[ep].diepint.b.inepnakeff));

        data->core->inep_regs[ep].diepctl.b.epdis = 1;

static struct ep_type endpoints[5];

        while (!(data->core->inep_regs[ep].diepint.b.epdisabled));

static struct usb_ctrlrequest ctrlreq CACHEALIGN_ATTR;

        if (ep) data->core->inep_regs[ep].diepctl.b.usbactep = 0;

static struct scheduler_thread synopsysotg_thread_handle;

        synopsysotg_target_enable_irq(instance);

static uint32_t synopsysotg_stack[0x40] STACK_ATTR;

        // Wait for any DMA activity to stop, to make sure nobody will touch the FIFO.

        while (!data->core->gregs.grstctl.b.ahbidle);

int usb_drv_port_speed(void)

        // Flush it all the way down!

{

        union synopsysotg_grstctl grstctl = { .b = { .txfnum = data->core->inep_regs[ep].diepctl.b.txfnum, .txfflsh = 1 } };

    return (DSTS & 2) == 0 ? 1 : 0;

        data->core->gregs.grstctl = grstctl;

}

        while (data->core->gregs.grstctl.b.txfflsh);

    }

static void reset_endpoints(int reinit)

    else if (ep) data->core->inep_regs[ep].diepctl.b.usbactep = 0;

{

    // Reset the transfer size register. Not strictly necessary, but can't hurt.

    unsigned int i;

    data->core->inep_regs[ep].dieptsiz.d32 = 0;

    for (i = 0; i < sizeof(endpoints)/sizeof(struct ep_type); i++)

}

    {

        if (reinit) endpoints[i].active = false;

static void synopsysotg_flush_ints(const struct usb_instance* instance)

        endpoints[i].busy = false;

{

        endpoints[i].rc = -1;

    const struct synopsysotg_config* data = (const struct synopsysotg_config*)instance->driver_config;

        endpoints[i].done = true;

    int i;

        wakeup_signal(&endpoints[i].complete);

    for (i = 0; i < 16; i++)

    }

    {

    DIEPCTL0 = 0x8800;  /* EP0 IN ACTIVE NEXT=1 */

        data->core->outep_regs[i].doepint = data->core->outep_regs[i].doepint;

    DOEPCTL0 = 0x8000;  /* EP0 OUT ACTIVE */

        data->core->inep_regs[i].diepint = data->core->inep_regs[i].diepint;

    DOEPTSIZ0 = 0x20080040;  /* EP0 OUT Transfer Size:

    }

                                64 Bytes, 1 Packet, 1 Setup Packet */

    data->core->gregs.gintsts = data->core->gregs.gintsts;

    DOEPDMA0 = &ctrlreq;

}

    DOEPCTL0 |= 0x84000000;  /* EP0 OUT ENABLE CLEARNAK */

    if (reinit)

static void synopsysotg_try_push(const struct usb_instance* instance, int ep)

    {

{

        /* The size is getting set to zero, because we don't know

    const struct synopsysotg_config* data = (const struct synopsysotg_config*)instance->driver_config;

           whether we are Full Speed or High Speed at this stage */

    struct synopsysotg_state* state = (struct synopsysotg_state*)instance->driver_state;

        /* EP1 IN INACTIVE DATA0 SIZE=0 NEXT=3 */

    union synopsysotg_depctl depctl = data->core->inep_regs[ep].diepctl;

        DIEPCTL1 = 0x10001800;

    if (!depctl.b.epena || !depctl.b.usbactep || depctl.b.stall || depctl.b.naksts) return;

        /* EP2 OUT INACTIVE DATA0 SIZE=0 */

    int bytesleft = data->core->inep_regs[ep].dieptsiz.b.xfersize;

        DOEPCTL2 = 0x10000000;

    if (!bytesleft) return;

        /* EP3 IN INACTIVE DATA0 SIZE=0 NEXT=0 */

    int maxpacket = ep ? data->core->inep_regs[ep].diepctl.b.mps : 64;

        DIEPCTL3 = 0x10000000;

    union synopsysotg_hnptxsts fifospace = data->core->gregs.hnptxsts;

        /* EP4 OUT INACTIVE DATA0 SIZE=0 */

    int words = (MIN(maxpacket, bytesleft) + 3) >> 2;

        DOEPCTL4 = 0x10000000;

    if (fifospace.b.nptxqspcavail && fifospace.b.nptxfspcavail << 2 >= words)

    }

        while (words--) data->core->dfifo[ep][0] = *state->endpoints[ep].txaddr++;

    else

    if (!words && bytesleft <= maxpacket) return;

    {

    data->core->gregs.gintmsk.b.nptxfempty = true;

        /* INACTIVE DATA0 */

}

        DIEPCTL1 = (DIEPCTL1 & ~0x00008000) | 0x10000000;

        DOEPCTL2 = (DOEPCTL2 & ~0x00008000) | 0x10000000;

void synopsysotg_start_rx(const struct usb_instance* instance, union usb_endpoint_number ep, void* buf, int size)

        DIEPCTL3 = (DIEPCTL3 & ~0x00008000) | 0x10000000;

{

        DOEPCTL4 = (DOEPCTL4 & ~0x00008000) | 0x10000000;

    const struct synopsysotg_config* data = (const struct synopsysotg_config*)instance->driver_config;

    }

    struct synopsysotg_state* state = (struct synopsysotg_state*)instance->driver_state;

    DAINTMSK = 0xFFFFFFFF;  /* Enable interrupts on all EPs */

}

    // Find the appropriate set of endpoint registers

    volatile struct synopsysotg_outepregs* regs = &data->core->outep_regs[ep.number];

int usb_drv_request_endpoint(int type, int dir)

    // Calculate number of packets (if size == 0 an empty packet will be sent)

{

    int maxpacket = regs->doepctl.b.mps;

    size_t ep;

    int packets = (size + maxpacket - 1) / maxpacket;

    int ret = -1;

    if (!packets) packets = 1;

    if (dir == USB_DIR_IN) ep = 1;

    // Set up data destination

    else ep = 2;

    if (data->use_dma) regs->doepdma = buf;

    else state->endpoints[ep.number].rxaddr = (uint32_t*)buf;

    while (ep < 5)

    union synopsysotg_depxfrsiz deptsiz = { .b = { .pktcnt = packets, .xfersize = size } };

    {

    regs->doeptsiz = deptsiz;

        if (!endpoints[ep].active)

        {

    // Flush CPU cache if necessary

            endpoints[ep].active = true;

    if (data->use_dma) invalidate_dcache(buf, size);

            ret = ep | dir;

            uint32_t newbits = (type << 18) | 0x10000000;

    // Enable the endpoint

            if (dir) DIEPCTL(ep) = (DIEPCTL(ep) & ~0x000C0000) | newbits;

    union synopsysotg_depctl depctl = regs->doepctl;

            else DOEPCTL(ep) = (DOEPCTL(ep) & ~0x000C0000) | newbits;

    depctl.b.epena = 1;

            break;

    depctl.b.cnak = 1;

        }

    regs->doepctl = depctl;

        ep += 2;

}

    }

void synopsysotg_start_tx(const struct usb_instance* instance, union usb_endpoint_number ep, const void* buf, int size)

    return ret;

{

}

    const struct synopsysotg_config* data = (const struct synopsysotg_config*)instance->driver_config;

    struct synopsysotg_state* state = (struct synopsysotg_state*)instance->driver_state;

void usb_drv_release_endpoint(int ep)

{

    // Find the appropriate set of endpoint registers

    ep = ep & 0x7f;

    volatile struct synopsysotg_inepregs* regs = &data->core->inep_regs[ep.number];

    // Calculate number of packets (if size == 0 an empty packet will be sent)

    if (ep < 1 || ep > USB_NUM_ENDPOINTS) return;

    int maxpacket = regs->diepctl.b.mps;

    int packets = (size + maxpacket - 1) / maxpacket;

    endpoints[ep].active = false;

    if (!packets) packets = 1;

}

    // Set up data source

static void usb_reset(void)

    if (data->use_dma) regs->diepdma = buf;

{

    else state->endpoints[ep.number].txaddr = (uint32_t*)buf;

    DCTL = 0x802;  /* Soft Disconnect */

    union synopsysotg_depxfrsiz deptsiz = { .b = { .pktcnt = packets, .xfersize = size } };

    regs->dieptsiz = deptsiz;

    OPHYPWR = 0;  /* PHY: Power up */

    udelay(10);

    // Flush CPU cache if necessary

    OPHYUNK1 = 1;

    if (data->use_dma) clean_dcache(buf, size);

    OPHYUNK2 = 0xE3F;

    ORSTCON = 1;  /* PHY: Assert Software Reset */

    // Enable the endpoint

    udelay(10);

    union synopsysotg_depctl depctl = regs->diepctl;

    ORSTCON = 0;  /* PHY: Deassert Software Reset */

    depctl.b.epena = 1;

    udelay(10);

    depctl.b.cnak = 1;

    OPHYUNK3 = 0x600;

    regs->diepctl = depctl;

    OPHYCLK = SYNOPSYSOTG_CLOCK;

    sleep(400);

    // Start pushing data into the FIFO (must be done after enabling the endpoint)

    if (size && !data->use_dma)

    GRSTCTL = 1;  /* OTG: Assert Software Reset */

    {

    while (GRSTCTL & 1);  /* Wait for OTG to ack reset */

        if (data->shared_txfifo) synopsysotg_try_push(instance, ep.number);

    while (!(GRSTCTL & 0x80000000));  /* Wait for OTG AHB master idle */

        else data->core->dregs.diepempmsk.ep.in |= (1 << ep.number);

    }

    GRXFSIZ = 0x00000200;  /* RX FIFO: 512 bytes */

}

    GNPTXFSIZ = 0x02000200;  /* Non-periodic TX FIFO: 512 bytes */

    GAHBCFG = SYNOPSYSOTG_AHBCFG;

int synopsysotg_get_stall(const struct usb_instance* instance, union usb_endpoint_number ep)

    GUSBCFG = 0x1408;  /* OTG: 16bit PHY and some reserved bits */

{

    const struct synopsysotg_config* data = (const struct synopsysotg_config*)instance->driver_config;

    DCFG = 4;  /* Address 0 */

    if (ep.direction == USB_ENDPOINT_DIRECTION_IN)

    DCTL = 0x800;  /* Soft Reconnect */

        return !!data->core->inep_regs[ep.number].diepctl.b.stall;

    DIEPMSK = 0x0D;  /* IN EP interrupt mask */

    return !!data->core->outep_regs[ep.number].doepctl.b.stall;

    DOEPMSK = 0x0D;  /* IN EP interrupt mask */

}

    DAINTMSK = 0xFFFFFFFF;  /* Enable interrupts on all endpoints */

    GINTMSK = 0xC3000;  /* Interrupt mask: IN event, OUT event, bus reset */

void synopsysotg_set_stall(const struct usb_instance* instance, union usb_endpoint_number ep, int stall)

{

    reset_endpoints(1);

    const struct synopsysotg_config* data = (const struct synopsysotg_config*)instance->driver_config;

}

    if (ep.direction == USB_ENDPOINT_DIRECTION_IN)

    {

/* IRQ handler */

        data->core->inep_regs[ep.number].diepctl.b.stall = !!stall;

void INT_USB_FUNC(void)

        if (!stall) data->core->inep_regs[ep.number].diepctl.b.setd0pid = true;

{

    }

    int i;

    else

    uint32_t ints = GINTSTS;

    {

    uint32_t epints;

        data->core->outep_regs[ep.number].doepctl.b.stall = !!stall;

    if (ints & 0x1000)  /* bus reset */

        if (!stall) data->core->outep_regs[ep.number].doepctl.b.setd0pid = true;

    {

    }

        DCFG = 4;  /* Address 0 */

        reset_endpoints(1);

}

        usb_handle_bus_reset();

    }

void synopsysotg_set_address(const struct usb_instance* instance, uint8_t address)

{

    if (ints & 0x2000)  /* enumeration done, we now know the speed */

    const struct synopsysotg_config* data = (const struct synopsysotg_config*)instance->driver_config;

    {

    data->core->dregs.dcfg.b.devaddr = address;

        /* Set up the maximum packet sizes accordingly */

}

        uint32_t maxpacket = usb_drv_port_speed() ? 512 : 64;

        DIEPCTL1 = (DIEPCTL1 & ~0x000003FF) | maxpacket;

void synopsysotg_unconfigure_ep(const struct usb_instance* instance, union usb_endpoint_number ep)

        DOEPCTL2 = (DOEPCTL2 & ~0x000003FF) | maxpacket;

{

        DIEPCTL3 = (DIEPCTL3 & ~0x000003FF) | maxpacket;

    const struct synopsysotg_config* data = (const struct synopsysotg_config*)instance->driver_config;

        DOEPCTL4 = (DOEPCTL4 & ~0x000003FF) | maxpacket;

    if (ep.direction == USB_ENDPOINT_DIRECTION_IN)

    }

    {

        // Kill any outstanding IN transfers

    if (ints & 0x40000)  /* IN EP event */

        synopsysotg_flush_in_endpoint(instance, ep.number);

        for (i = 0; i < 4; i += i + 1)  // 0, 1, 3

        // Mask interrupts for this endpoint

            if (epints = DIEPINT(i))

        data->core->dregs.daintmsk.ep.in &= ~(1 << ep.number);

            {

    }

                if (epints & 1)  /* Transfer completed */

    else

                {

    {

                    int bytes = endpoints[i].size - (DIEPTSIZ(i) & 0x3FFFF);

        // Kill any outstanding OUT transfers

                    if (endpoints[i].busy)

        synopsysotg_flush_out_endpoint(instance, ep.number);

                    {

        // Mask interrupts for this endpoint

                        endpoints[i].busy = false;

        data->core->dregs.daintmsk.ep.out &= ~(1 << ep.number);

                        endpoints[i].rc = 0;

    }

                        endpoints[i].done = true;

}

                        usb_handle_transfer_complete(i, USB_DIR_IN, 0, bytes);

                        wakeup_signal(&endpoints[i].complete);

void synopsysotg_configure_ep(const struct usb_instance* instance, union usb_endpoint_number ep,

                    }

                              enum usb_endpoint_type type, int maxpacket)

                }

{

                if (epints & 4)  /* AHB error */

    const struct synopsysotg_config* data = (const struct synopsysotg_config*)instance->driver_config;

                    panicf(PANIC_FATAL, "USB: AHB error on IN EP%d", i);

                if (epints & 8)  /* Timeout */

    // Write the new configuration and unmask interrupts for the endpoint.

                {

    // Reset data toggle to DATA0, as required by the USB specification.

                    if (endpoints[i].busy)

    int txfifo = data->shared_txfifo ? 0 : ep.number;

                    {

    union synopsysotg_depctl depctl = { .b = { .usbactep = 1, .eptype = type, .mps = maxpacket,

                        endpoints[i].busy = false;

                                               .txfnum = txfifo, .setd0pid = 1, .nextep = (ep.number + 1) & 0xf } };

                        endpoints[i].rc = 1;

    if (ep.direction == USB_ENDPOINT_DIRECTION_IN)

                        endpoints[i].done = true;

    {

                        wakeup_signal(&endpoints[i].complete);

        data->core->inep_regs[ep.number].diepctl = depctl;

                    }

        data->core->dregs.daintmsk.ep.in |= (1 << ep.number);

                }

    }

                DIEPINT(i) = epints;

    else

            }

    {

        data->core->outep_regs[ep.number].doepctl = depctl;

    if (ints & 0x80000)  /* OUT EP event */

        data->core->dregs.daintmsk.ep.out |= (1 << ep.number);

        for (i = 0; i < 5; i += 2)  // 0, 2, 4

    }

            if (epints = DOEPINT(i))

}

            {

                if (epints & 1)  /* Transfer completed */

void synopsysotg_ep0_start_rx(const struct usb_instance* instance, int non_setup)

                {

{

                    int bytes = endpoints[i].size - (DOEPTSIZ(i) & 0x3FFFF);

    const struct synopsysotg_config* data = (const struct synopsysotg_config*)instance->driver_config;

                    if (endpoints[i].busy)

    struct synopsysotg_state* state = (struct synopsysotg_state*)instance->driver_state;

                    {

                        endpoints[i].busy = false;

    // Set up data destination

                        endpoints[i].rc = 0;

    if (data->use_dma) data->core->outep_regs[0].doepdma = instance->buffer;

                        endpoints[i].done = true;

    else state->endpoints[0].rxaddr = (uint32_t*)instance->buffer;

                        usb_handle_transfer_complete(i, USB_DIR_OUT, 0, bytes);

    union synopsysotg_dep0xfrsiz deptsiz = { .b = { .supcnt = 3, .pktcnt = !!non_setup, .xfersize = 64 } };

                        wakeup_signal(&endpoints[i].complete);

    data->core->outep_regs[0].doeptsiz.d32 = deptsiz.d32;

                    }

                }

    // Flush CPU cache if necessary

                if (epints & 4)  /* AHB error */

    if (data->use_dma) invalidate_dcache(instance->buffer, sizeof(instance->buffer));

                    panicf(PANIC_FATAL, "USB: AHB error on OUT EP%d", i);

                if (epints & 8)  /* SETUP phase done */

    // Enable the endpoint

                {

    union synopsysotg_depctl depctl = data->core->outep_regs[0].doepctl;

                    invalidate_dcache();

    depctl.b.epena = 1;

                    if (i == 0) usb_handle_control_request(&ctrlreq);

    depctl.b.cnak = non_setup;

                    else panicf(PANIC_FATAL, "USB: SETUP done on OUT EP%d!?", i);

    data->core->outep_regs[0].doepctl = depctl;

                }

}

                /* Make sure EP0 OUT is set up to accept the next request */

                if (!i)

void synopsysotg_ep0_start_tx(const struct usb_instance* instance, const void* buf, int len)

                {

{

                    DOEPTSIZ0 = 0x20080040;

    const struct synopsysotg_config* data = (const struct synopsysotg_config*)instance->driver_config;

                    DOEPDMA0 = &ctrlreq;

    struct synopsysotg_state* state = (struct synopsysotg_state*)instance->driver_state;

                    DOEPCTL0 |= 0x84000000;

                }

    if (len)

                DOEPINT(i) = epints;

    {

            }

        // Set up data source

        if (data->use_dma) data->core->inep_regs[0].diepdma = buf;

    GINTSTS = ints;

        else state->endpoints[0].txaddr = buf;

}

        union synopsysotg_dep0xfrsiz deptsiz = { .b = { .pktcnt = (len + 63) >> 6, .xfersize = len } };

        data->core->inep_regs[0].dieptsiz.d32 = deptsiz.d32;

void usb_drv_set_address(int address)

    }

{

    else

    DCFG = (DCFG & ~0x7F0) | (address << 4);

    {

}

        // Set up the IN pipe for a zero-length packet

        union synopsysotg_dep0xfrsiz deptsiz = { .b = { .pktcnt = 1 } };

static void ep_send(int ep, const void *ptr, int length)

        data->core->inep_regs[0].dieptsiz.d32 = deptsiz.d32;

{

    }

    endpoints[ep].busy = true;

    endpoints[ep].size = length;

    // Flush CPU cache if necessary

    DIEPCTL(ep) |= 0x8000;  /* EPx OUT ACTIVE */

    if (data->use_dma) clean_dcache(buf, len);

    int blocksize = usb_drv_port_speed() ? 512 : 64;

    int packets = (length + blocksize - 1) / blocksize;

    // Enable the endpoint

    if (!length)

    union synopsysotg_depctl depctl = data->core->inep_regs[0].diepctl;

    {

    depctl.b.epena = 1;

        DIEPTSIZ(ep) = 1 << 19;  /* one empty packet */

    depctl.b.cnak = 1;

        DIEPDMA(ep) = NULL;  /* dummy address */

    data->core->inep_regs[0].diepctl = depctl;

    }

    else

    // Start pushing data into the FIFO (must be done after enabling the endpoint)

    {

    if (len && !data->use_dma)

        DIEPTSIZ(ep) = length | (packets << 19);

    {

        DIEPDMA(ep) = ptr;

        if (data->shared_txfifo) synopsysotg_try_push(instance, 0);

    }

        else data->core->dregs.diepempmsk.ep.in |= 1;

    clean_dcache();

    }

    DIEPCTL(ep) |= 0x84000000;  /* EPx OUT ENABLE CLEARNAK */

}

}

static void synopsysotg_ep0_init(const struct usb_instance* instance)

static void ep_recv(int ep, void *ptr, int length)

{

{

    const struct synopsysotg_config* data = (const struct synopsysotg_config*)instance->driver_config;

    endpoints[ep].busy = true;

    endpoints[ep].size = length;

    // Make sure both EP0 pipes are active.

    DOEPCTL(ep) &= ~0x20000;  /* EPx UNSTALL */

    // (The hardware should take care of that, but who knows...)

    DOEPCTL(ep) |= 0x8000;  /* EPx OUT ACTIVE */

    union synopsysotg_depctl depctl = { .b = { .usbactep = 1, .nextep = data->core->inep_regs[0].diepctl.b.nextep } };

    int blocksize = usb_drv_port_speed() ? 512 : 64;

    data->core->outep_regs[0].doepctl = depctl;

    int packets = (length + blocksize - 1) / blocksize;

    data->core->inep_regs[0].diepctl = depctl;

    if (!length)

}

    {

        DOEPTSIZ(ep) = 1 << 19;  /* one empty packet */

void synopsysotg_irq(const struct usb_instance* instance)

        DOEPDMA(ep) = NULL;  /* dummy address */

{

    }

    const struct synopsysotg_config* data = (const struct synopsysotg_config*)instance->driver_config;

    else

    struct synopsysotg_state* state = (struct synopsysotg_state*)instance->driver_state;

    {

        DOEPTSIZ(ep) = length | (packets << 19);

    union synopsysotg_gintsts gintsts = data->core->gregs.gintsts;

        DOEPDMA(ep) = ptr;

    }

    if (gintsts.b.usbreset)

    invalidate_dcache();

    {

    DOEPCTL(ep) |= 0x84000000;  /* EPx OUT ENABLE CLEARNAK */

        data->core->dregs.dcfg.b.devaddr = 0;

}

        usb_handle_bus_reset(instance, 0);

    }

int usb_drv_send(int endpoint, const void *ptr, int length)

{

    if (gintsts.b.enumdone)

    endpoint &= 0x7f;

    {

    endpoints[endpoint].done = false;

        usb_handle_bus_reset(instance, data->core->dregs.dsts.b.enumspd == 0);

    ep_send(endpoint, ptr, length);

        synopsysotg_ep0_init(instance);

    while (!endpoints[endpoint].done && endpoints[endpoint].busy)

    }

        wakeup_wait(&endpoints[endpoint].complete, TIMEOUT_BLOCK);

    return endpoints[endpoint].rc;

    if (gintsts.b.rxstsqlvl && !data->use_dma)

}

    {

        // Device to memory part of the "software DMA" implementation, used to receive data if use_dma == 0.

int usb_drv_send_nonblocking(int endpoint, const void *ptr, int length)

        // Handle one packet at a time, the IRQ will re-trigger if there's something left.

{

        union synopsysotg_grxfsts rxsts = data->core->gregs.grxstsp;

    ep_send(endpoint & 0x7f, ptr, length);

        int ep = rxsts.b.chnum;

    return 0;

        int words = (rxsts.b.bcnt + 3) >> 2;

}

        while (words--) *state->endpoints[ep].rxaddr++ = data->core->dfifo[0][0];

    }

int usb_drv_recv(int endpoint, void* ptr, int length)

{

    if (gintsts.b.nptxfempty && data->core->gregs.gintmsk.b.nptxfempty)

    ep_recv(endpoint & 0x7f, ptr, length);

    {

    return 0;

        // Old style, "shared TX FIFO" memory to device part of the "software DMA" implementation,

}

        // used to send data if use_dma == 0 and the device doesn't support one non-periodic TX FIFO per endpoint.

void usb_drv_cancel_all_transfers(void)

        // First disable the IRQ, it will be re-enabled later if there is anything left to be done.

{

        data->core->gregs.gintmsk.b.nptxfempty = false;

    uint32_t mode = enter_critical_section();

    reset_endpoints(0);

        // Check all endpoints for anything to be transmitted

    leave_critical_section(mode);

        int ep;

}

        for (ep = 0; ep < 16; ep++) synopsysotg_try_push(instance, ep);

    }

bool usb_drv_stalled(int endpoint, bool in)

{

    if (gintsts.b.inepintr)

    if (in) return DIEPCTL(endpoint) & 0x00200000 ? true : false;

    {

    else return DOEPCTL(endpoint) & 0x00200000 ? true : false;

        union synopsysotg_daint daint = data->core->dregs.daint;

}

        int ep;

        for (ep = 0; ep < 16; ep++)

void usb_drv_stall(int endpoint, bool stall, bool in)

            if (daint.ep.in & (1 << ep))

{

            {

    if (in)

                union synopsysotg_diepintn epints = data->core->inep_regs[ep].diepint;

    {

                if (epints.b.emptyintr)

        if (stall) DIEPCTL(endpoint) |= 0x00200000;

                {

        else DIEPCTL(endpoint) &= ~0x00200000;

                    // Memory to device part of the "software DMA" implementation, used to transmit data if use_dma == 0.

    }

                    union synopsysotg_depxfrsiz deptsiz = data->core->inep_regs[ep].dieptsiz;

    else

                    if (!deptsiz.b.xfersize) data->core->dregs.diepempmsk.ep.in &= ~(1 << ep);

    {

                    else

        if (stall) DOEPCTL(endpoint) |= 0x00200000;

                    {

        else DOEPCTL(endpoint) &= ~0x00200000;

                        // Push data into the TX FIFO until we don't have anything left or the FIFO would overflow.

    }

                        int left = (deptsiz.b.xfersize + 3) >> 2;

}

                        while (left)

                        {

void usb_drv_power_up(void)

                            int words = data->core->inep_regs[ep].dtxfsts.b.txfspcavail;

{

                            if (words > left) words = left;

    /* Enable USB clock */

                            if (!words) break;

    clockgate_enable(CLOCKGATE_USB_1, true);

                            left -= words;

    clockgate_enable(CLOCKGATE_USB_2, true);

                            while (words--) data->core->dfifo[ep][0] = *state->endpoints[ep].txaddr++;

    PCGCCTL = 0;

                        }

                    }

    /* reset the beast */

                }

    usb_reset();

                union usb_endpoint_number epnum = { .direction = USB_ENDPOINT_DIRECTION_IN, .number = ep };

}

                int bytesleft = data->core->inep_regs[ep].dieptsiz.b.xfersize;

                if (epints.b.timeout) usb_handle_timeout(instance, epnum, bytesleft);

void usb_drv_power_down(void)

                if (epints.b.xfercompl) usb_handle_xfer_complete(instance, epnum, bytesleft);

{

                data->core->inep_regs[ep].diepint = epints;

    DCTL = 0x802;  /* Soft Disconnect */

            }

    }

    OPHYPWR = 0xF;  /* PHY: Power down */

    udelay(10);

    if (gintsts.b.outepintr)

    ORSTCON = 7;  /* Put the PHY into reset (needed to get current down) */

    {

    udelay(10);

        union synopsysotg_daint daint = data->core->dregs.daint;

    PCGCCTL = 1;  /* Shut down PHY clock */

        int ep;

        for (ep = 0; ep < 16; ep++)

    clockgate_enable(CLOCKGATE_USB_1, false);

            if (daint.ep.out & (1 << ep))

    clockgate_enable(CLOCKGATE_USB_2, false);

            {

}

                union synopsysotg_doepintn epints = data->core->outep_regs[ep].doepint;

                union usb_endpoint_number epnum = { .direction = USB_ENDPOINT_DIRECTION_OUT, .number = ep };

void usb_check_vbus(void* arg0, void* arg1, void* arg2, void* arg3)

                if (epints.b.setup)

{

                {

    bool oldstate = false;

                    if (data->use_dma) invalidate_dcache(instance->buffer, sizeof(instance->buffer));

    while (true)

                    synopsysotg_flush_in_endpoint(instance, ep);

    {

                    usb_handle_setup_received(instance, epnum);

        sleep(200000);

                }

        bool newstate = vbus_state();

                else if (epints.b.xfercompl)

        if (oldstate != newstate)

                {

        {

                    int bytesleft = data->core->inep_regs[ep].dieptsiz.b.xfersize;

            if (newstate) usb_drv_power_up();

                    usb_handle_xfer_complete(instance, epnum, bytesleft);

            else usb_drv_power_down();

                }

            oldstate = newstate;

                data->core->outep_regs[ep].doepint = epints;

        }

            }

    }

    }

}

    data->core->gregs.gintsts = gintsts;

void usb_drv_init(void)

}

{

    unsigned int i;

void synopsysotg_init(const struct usb_instance* instance)

    for (i = 0; i < sizeof(endpoints)/sizeof(struct ep_type); i++)

{

        wakeup_init(&endpoints[i].complete);

    int i;

    /* Enable USB clock */

    const struct synopsysotg_config* data = (const struct synopsysotg_config*)instance->driver_config;

    clockgate_enable(CLOCKGATE_USB_1, true);

    clockgate_enable(CLOCKGATE_USB_2, true);

    // Disable IRQ during setup

    PCGCCTL = 0;

    synopsysotg_target_disable_irq(instance);

    /* unmask irq */

    // Enable OTG clocks

    interrupt_enable(IRQ_USB_FUNC, true);

    synopsysotg_target_enable_clocks(instance);

    thread_create(&synopsysotg_thread_handle, "synopsysotg", usb_check_vbus,

    // Enable PHY clocks

                  synopsysotg_stack, sizeof(synopsysotg_stack), OS_THREAD, 63, true,

    union synopsysotg_pcgcctl pcgcctl = { .b = {} };

                  NULL, NULL, NULL, NULL);

    data->core->pcgcctl = pcgcctl;

    usb_drv_power_down();

    // Configure PHY type (must be done before reset)

}

    union synopsysotg_gccfg gccfg = { .b = { .disablevbussensing = 1, .pwdn = 0 } };

    data->core->gregs.gccfg = gccfg;

void usb_drv_exit(void)

    union synopsysotg_gusbcfg gusbcfg = { .b = { .force_dev = 1, .usbtrdtim = SYNOPSYSOTG_TURNAROUND } };

{

    if (data->phy_16bit) gusbcfg.b.phyif = 1;

    usb_drv_power_down();

    else if (data->phy_ulpi) gusbcfg.b.ulpi_utmi_sel = 1;

}

    else gusbcfg.b.physel  = 1;

    data->core->gregs.gusbcfg = gusbcfg;

int usb_drv_get_max_out_size()

{

    // Reset the whole USB core

    return usb_drv_port_speed() ? 262144 : 32768;

    union synopsysotg_grstctl grstctl = { .b = { .csftrst = 1 } };

}

    udelay(100);

    while (!data->core->gregs.grstctl.b.ahbidle);

int usb_drv_get_max_in_size()

    data->core->gregs.grstctl = grstctl;

{

    while (data->core->gregs.grstctl.b.csftrst);

    return usb_drv_port_speed() ? 262144 : 32768;

    while (!data->core->gregs.grstctl.b.ahbidle);

}