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Line 134... Line 134...
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static void usb_reset(void)
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static void usb_reset(void)
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{
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{
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    DCTL = 0x802;  /* Soft Disconnect */
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    DCTL = 0x802;  /* Soft Disconnect */
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    OPHYPWR = 0;  /* PHY: Power up */
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    OPHYPWR = 0;  /* PHY: Power up */
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    udelay(10);
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    OPHYUNK1 = 1;
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    OPHYUNK1 = 1;
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    OPHYUNK2 = 0xE3F;
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    OPHYUNK2 = 0xE3F;
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    OPHYCLK = SYNOPSYSOTG_CLOCK;
 - 
 
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    ORSTCON = 1;  /* PHY: Assert Software Reset */
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    ORSTCON = 1;  /* PHY: Assert Software Reset */
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    udelay(10);
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    udelay(10);
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    ORSTCON = 0;  /* PHY: Deassert Software Reset */
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    ORSTCON = 0;  /* PHY: Deassert Software Reset */
- 
 
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    udelay(10);
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    OPHYUNK3 = 0x600;
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    OPHYUNK3 = 0x600;
- 
 
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    OPHYCLK = SYNOPSYSOTG_CLOCK;
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    sleep(400);
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    GRSTCTL = 1;  /* OTG: Assert Software Reset */
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    GRSTCTL = 1;  /* OTG: Assert Software Reset */
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    while (GRSTCTL & 1);  /* Wait for OTG to ack reset */
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    while (GRSTCTL & 1);  /* Wait for OTG to ack reset */
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    while (!(GRSTCTL & 0x80000000));  /* Wait for OTG AHB master idle */
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    while (!(GRSTCTL & 0x80000000));  /* Wait for OTG AHB master idle */
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Line 364... Line 367...
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void usb_drv_power_down(void)
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void usb_drv_power_down(void)
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{
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{
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    DCTL = 0x802;  /* Soft Disconnect */
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    DCTL = 0x802;  /* Soft Disconnect */
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    ORSTCON = 1;  /* Put the PHY into reset (needed to get current down) */
 - 
 
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    PCGCCTL = 1;  /* Shut down PHY clock */
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    OPHYPWR = 0xF;  /* PHY: Power down */
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    OPHYPWR = 0xF;  /* PHY: Power down */
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    udelay(10);
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    ORSTCON = 7;  /* Put the PHY into reset (needed to get current down) */
- 
 
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    udelay(10);
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    PCGCCTL = 1;  /* Shut down PHY clock */
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    clockgate_enable(CLOCKGATE_USB_1, false);
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    clockgate_enable(CLOCKGATE_USB_1, false);
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    clockgate_enable(CLOCKGATE_USB_2, false);
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    clockgate_enable(CLOCKGATE_USB_2, false);
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}
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}
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