WebSVN – freemyipod – Diff – /emcore/trunk/target/ipodnano3g/s5l8702.h

 #define ATA_FIFO_STATUS     (*((uint32_t volatile*)(0x38700084)))
 #define ATA_DMA_ADDR        (*((void* volatile*)(0x38700088)))
 /////SDCI/////
 #define SDCI_CTRL     (*((uint32_t volatile*)(0x38b00000)))
 #define SDCI_DCTRL    (*((uint32_t volatile*)(0x38b00004)))
 #define SDCI_CMD      (*((uint32_t volatile*)(0x38b00008)))
 #define SDCI_ARGU     (*((uint32_t volatile*)(0x38b0000c)))
 #define SDCI_STATE    (*((uint32_t volatile*)(0x38b00010)))
 #define SDCI_STAC     (*((uint32_t volatile*)(0x38b00014)))
 #define SDCI_DSTA     (*((uint32_t volatile*)(0x38b00018)))
 #define SDCI_FSTA     (*((uint32_t volatile*)(0x38b0001c)))
 #define SDCI_RESP0    (*((uint32_t volatile*)(0x38b00020)))
 #define SDCI_RESP1    (*((uint32_t volatile*)(0x38b00024)))
 #define SDCI_RESP2    (*((uint32_t volatile*)(0x38b00028)))
 #define SDCI_RESP3    (*((uint32_t volatile*)(0x38b0002c)))
 #define SDCI_CDIV     (*((uint32_t volatile*)(0x38b00030)))
 #define SDCI_SDIO_CSR (*((uint32_t volatile*)(0x38b00034)))
 #define SDCI_IRQ      (*((uint32_t volatile*)(0x38b00038)))
 #define SDCI_IRQ_MASK (*((uint32_t volatile*)(0x38b0003c)))
 #define SDCI_DATA     (*((uint32_t volatile*)(0x38b00040)))
 #define SDCI_DMAADDR  (*((void* volatile*)(0x38b00044)))
 #define SDCI_DMASIZE  (*((uint32_t volatile*)(0x38b00048)))
 #define SDCI_DMACOUNT (*((uint32_t volatile*)(0x38b0004c)))
 #define SDCI_RESET    (*((uint32_t volatile*)(0x38b0006c)))
 #define SDCI_CTRL_SDCIEN BIT(0)
 #define SDCI_CTRL_CARD_TYPE_MASK BIT(1)
 #define SDCI_CTRL_CARD_TYPE_SD 0
 #define SDCI_CTRL_CARD_TYPE_MMC BIT(1)
 #define SDCI_CTRL_BUS_WIDTH_MASK BITRANGE(2, 3)
 #define SDCI_CTRL_BUS_WIDTH_1BIT 0
 #define SDCI_CTRL_BUS_WIDTH_4BIT BIT(2)
 #define SDCI_CTRL_BUS_WIDTH_8BIT BIT(3)
 #define SDCI_CTRL_DMA_EN BIT(4)
 #define SDCI_CTRL_L_ENDIAN BIT(5)
 #define SDCI_CTRL_DMA_REQ_CON_MASK BIT(6)
 #define SDCI_CTRL_DMA_REQ_CON_NEMPTY 0
 #define SDCI_CTRL_DMA_REQ_CON_FULL BIT(6)
 #define SDCI_CTRL_CLK_SEL_MASK BIT(7)
 #define SDCI_CTRL_CLK_SEL_PCLK 0
 #define SDCI_CTRL_CLK_SEL_SDCLK BIT(7)
 #define SDCI_CTRL_BIT_8 BIT(8)
 #define SDCI_CTRL_BIT_14 BIT(14)
 #define SDCI_DCTRL_TXFIFORST BIT(0)
 #define SDCI_DCTRL_RXFIFORST BIT(1)
 #define SDCI_DCTRL_TRCONT_MASK BITRANGE(4, 5)
 #define SDCI_DCTRL_TRCONT_TX BIT(4)
 #define SDCI_DCTRL_BUS_TEST_MASK BITRANGE(6, 7)
 #define SDCI_DCTRL_BUS_TEST_TX BIT(6)
 #define SDCI_DCTRL_BUS_TEST_RX BIT(7)
 #define SDCI_CDIV_CLKDIV_MASK BITRANGE(0, 7)
 #define SDCI_CDIV_CLKDIV(x) ((x) >> 1)
 #define SDCI_CDIV_CLKDIV_2 BIT(0)
 #define SDCI_CDIV_CLKDIV_4 BIT(1)
 #define SDCI_CDIV_CLKDIV_8 BIT(2)
 #define SDCI_CDIV_CLKDIV_16 BIT(3)
 #define SDCI_CDIV_CLKDIV_32 BIT(4)
 #define SDCI_CDIV_CLKDIV_64 BIT(5)
 #define SDCI_CDIV_CLKDIV_128 BIT(6)
 #define SDCI_CDIV_CLKDIV_256 BIT(7)
 #define SDCI_CMD_CMD_NUM_MASK BITRANGE(0, 5)
 #define SDCI_CMD_CMD_NUM_SHIFT 0
 #define SDCI_CMD_CMD_NUM(x) (x)
 #define SDCI_CMD_CMD_TYPE_MASK BITRANGE(6, 7)
 #define SDCI_CMD_CMD_TYPE_BC 0
 #define SDCI_CMD_CMD_TYPE_BCR BIT(6)
 #define SDCI_CMD_CMD_TYPE_AC BIT(7)
 #define SDCI_CMD_CMD_TYPE_ADTC (BIT(6) | BIT(7))
 #define SDCI_CMD_CMD_RD_WR BIT(8)
 #define SDCI_CMD_RES_TYPE_MASK BITRANGE(16, 18)
 #define SDCI_CMD_RES_TYPE_NONE 0
 #define SDCI_CMD_RES_TYPE_R1 BIT(16)
 #define SDCI_CMD_RES_TYPE_R2 BIT(17)
 #define SDCI_CMD_RES_TYPE_R3 (BIT(16) | BIT(17))
 #define SDCI_CMD_RES_TYPE_R4 BIT(18)
 #define SDCI_CMD_RES_TYPE_R5 (BIT(16) | BIT(18))
 #define SDCI_CMD_RES_TYPE_R6 (BIT(17) | BIT(18))
 #define SDCI_CMD_RES_BUSY BIT(19)
 #define SDCI_CMD_RES_SIZE_MASK BIT(20)
 #define SDCI_CMD_RES_SIZE_48 0
 #define SDCI_CMD_RES_SIZE_136 BIT(20)
 #define SDCI_CMD_NCR_NID_MASK BIT(21)
 #define SDCI_CMD_NCR_NID_NCR 0
 #define SDCI_CMD_NCR_NID_NID BIT(21)
 #define SDCI_CMD_CMDSTR BIT(31)
 #define SDCI_STATE_DAT_STATE_MASK BITRANGE(0, 3)
 #define SDCI_STATE_DAT_STATE_IDLE 0
 #define SDCI_STATE_DAT_STATE_DAT_RCV BIT(0)
 #define SDCI_STATE_DAT_STATE_CRC_RCV BIT(1)
 #define SDCI_STATE_DAT_STATE_DAT_END (BIT(0) | BIT(1))
 #define SDCI_STATE_DAT_STATE_DAT_SET BIT(2)
 #define SDCI_STATE_DAT_STATE_DAT_OUT (BIT(0) | BIT(2))
 #define SDCI_STATE_DAT_STATE_CRC_TIME (BIT(1) | BIT(2))
 #define SDCI_STATE_DAT_STATE_CRC_OUT (BIT(0) | BIT(1) | BIT(2))
 #define SDCI_STATE_DAT_STATE_ENDB_OUT BIT(3)
 #define SDCI_STATE_DAT_STATE_ENDB_STOD (BIT(0) | BIT(3))
 #define SDCI_STATE_DAT_STATE_DAT_CRCR (BIT(1) | BIT(3))
 #define SDCI_STATE_DAT_STATE_CARD_PRG (BIT(0) | BIT(1) | BIT(3))
 #define SDCI_STATE_DAT_STATE_DAT_BUSY (BIT(2) | BIT(3))
 #define SDCI_STATE_CMD_STATE_MASK (BIT(4) | BIT(5) | BIT(6))
 #define SDCI_STATE_CMD_STATE_CMD_IDLE 0
 #define SDCI_STATE_CMD_STATE_CMD_CMDO BIT(4)
 #define SDCI_STATE_CMD_STATE_CMD_CRCO BIT(5)
 #define SDCI_STATE_CMD_STATE_CMD_TOUT (BIT(4) | BIT(5))
 #define SDCI_STATE_CMD_STATE_CMD_RESR BIT(6)
 #define SDCI_STATE_CMD_STATE_CMD_INTV (BIT(4) | BIT(6))
 #define SDCI_STAC_CLR_CMDEND BIT(2)
 #define SDCI_STAC_CLR_BIT_3 BIT(3)
 #define SDCI_STAC_CLR_RESEND BIT(4)
 #define SDCI_STAC_CLR_DATEND BIT(6)
 #define SDCI_STAC_CLR_DAT_CRCEND BIT(7)
 #define SDCI_STAC_CLR_CRC_STAEND BIT(8)
 #define SDCI_STAC_CLR_RESTOUTE BIT(15)
 #define SDCI_STAC_CLR_RESENDE BIT(16)
 #define SDCI_STAC_CLR_RESINDE BIT(17)
 #define SDCI_STAC_CLR_RESCRCE BIT(18)
 #define SDCI_STAC_CLR_WR_DATCRCE BIT(22)
 #define SDCI_STAC_CLR_RD_DATCRCE BIT(23)
 #define SDCI_STAC_CLR_RD_DATENDE0 BIT(24)
 #define SDCI_STAC_CLR_RD_DATENDE1 BIT(25)
 #define SDCI_STAC_CLR_RD_DATENDE2 BIT(26)
 #define SDCI_STAC_CLR_RD_DATENDE3 BIT(27)
 #define SDCI_STAC_CLR_RD_DATENDE4 BIT(28)
 #define SDCI_STAC_CLR_RD_DATENDE5 BIT(29)
 #define SDCI_STAC_CLR_RD_DATENDE6 BIT(30)
 #define SDCI_STAC_CLR_RD_DATENDE7 BIT(31)
 #define SDCI_DSTA_CMDRDY BIT(0)
 #define SDCI_DSTA_CMDPRO BIT(1)
 #define SDCI_DSTA_CMDEND BIT(2)
 #define SDCI_DSTA_RESPRO BIT(3)
 #define SDCI_DSTA_RESEND BIT(4)
 #define SDCI_DSTA_DATPRO BIT(5)
 #define SDCI_DSTA_DATEND BIT(6)
 #define SDCI_DSTA_DAT_CRCEND BIT(7)
 #define SDCI_DSTA_CRC_STAEND BIT(8)
 #define SDCI_DSTA_DAT_BUSY BIT(9)
 #define SDCI_DSTA_SDCLK_HOLD BIT(12)
 #define SDCI_DSTA_DAT0_STATUS BIT(13)
 #define SDCI_DSTA_WP_DECT_INPUT BIT(14)
 #define SDCI_DSTA_RESTOUTE BIT(15)
 #define SDCI_DSTA_RESENDE BIT(16)
 #define SDCI_DSTA_RESINDE BIT(17)
 #define SDCI_DSTA_RESCRCE BIT(18)
 #define SDCI_DSTA_WR_CRC_STATUS_MASK BITRANGE(19, 21)
 #define SDCI_DSTA_WR_CRC_STATUS_OK BIT(20)
 #define SDCI_DSTA_WR_CRC_STATUS_TXERR (BIT(19) | BIT(21))
 #define SDCI_DSTA_WR_CRC_STATUS_CARDERR (BIT(19) | BIT(20) | BIT(21))
 #define SDCI_DSTA_WR_DATCRCE BIT(22)
 #define SDCI_DSTA_RD_DATCRCE BIT(23)
 #define SDCI_DSTA_RD_DATENDE0 BIT(24)
 #define SDCI_DSTA_RD_DATENDE1 BIT(25)
 #define SDCI_DSTA_RD_DATENDE2 BIT(26)
 #define SDCI_DSTA_RD_DATENDE3 BIT(27)
 #define SDCI_DSTA_RD_DATENDE4 BIT(28)
 #define SDCI_DSTA_RD_DATENDE5 BIT(29)
 #define SDCI_DSTA_RD_DATENDE6 BIT(30)
 #define SDCI_DSTA_RD_DATENDE7 BIT(31)
 #define SDCI_FSTA_RX_FIFO_EMPTY BIT(0)
 #define SDCI_FSTA_RX_FIFO_FULL BIT(1)
 #define SDCI_FSTA_TX_FIFO_EMPTY BIT(2)
 #define SDCI_FSTA_TX_FIFO_FULL BIT(3)
 #define SDCI_SDIO_CSR_SDIO_RW_EN BIT(0)
 #define SDCI_SDIO_CSR_SDIO_INT_EN BIT(1)
 #define SDCI_SDIO_CSR_SDIO_RW_REQ BIT(2)
 #define SDCI_SDIO_CSR_SDIO_RW_STOP BIT(3)
 #define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MASK BIT(4)
 #define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MORE 0
 #define SDCI_SDIO_CSR_SDIO_INT_PERIOD_XACT BIT(4)
 #define SDCI_IRQ_DAT_DONE_INT BIT(0)
 #define SDCI_IRQ_IOCARD_IRQ_INT BIT(1)
 #define SDCI_IRQ_READ_WAIT_INT BIT(2)
 #define SDCI_IRQ_MASK_MASK_DAT_DONE_INT BIT(0)
 #define SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT BIT(1)
 #define SDCI_IRQ_MASK_MASK_READ_WAIT_INT BIT(2)
 /////CLICKWHEEL/////
 #define WHEEL00      (*((uint32_t volatile*)(0x3C200000)))
 #define WHEEL04      (*((uint32_t volatile*)(0x3C200004)))
 #define WHEEL08      (*((uint32_t volatile*)(0x3C200008)))

Subversion Repositories freemyipod

(root)/emcore/trunk/target/ipodnano3g/s5l8702.h @ 660 – Rev 629 → 642