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Line 90... Line 90...
90
#ifdef ATA_HAVE_BBT
90
#ifdef ATA_HAVE_BBT
91
    .bbt_translate = ata_bbt_translate,
91
    .bbt_translate = ata_bbt_translate,
92
    .bbt_reload = ata_bbt_reload,
92
    .bbt_reload = ata_bbt_reload,
93
    .bbt_disable = ata_bbt_disable,
93
    .bbt_disable = ata_bbt_disable,
94
#endif
94
#endif
-
 
95
    .soft_reset = ata_soft_reset,
-
 
96
    .hard_reset = ata_hard_reset,
-
 
97
    .read_taskfile = ata_read_taskfile,
-
 
98
    .raw_cmd = ata_raw_cmd,
95
};
99
};
96
 
100
 
97
 
101
 
98
void ata_set_retries(int retries)
102
void ata_set_retries(int retries)
99
{
103
{
Line 463... Line 467...
463
                             0, NULL, CEATA_COMMAND_TIMEOUT), 1, 0);
467
                             0, NULL, CEATA_COMMAND_TIMEOUT), 1, 0);
464
    PASS_RC(ceata_wait_idle(), 1, 1);
468
    PASS_RC(ceata_wait_idle(), 1, 1);
465
    return 0;
469
    return 0;
466
}
470
}
467
 
471
 
468
int ceata_rw_multiple_block(bool write, void* buf, uint32_t count, long timeout)
472
int ceata_rw_multiple_block(bool write, void* buf, uint32_t count, uint32_t blksize, long timeout)
469
{
473
{
470
    mmc_discard_irq();
474
    mmc_discard_irq();
471
    uint32_t responsetype;
475
    uint32_t responsetype;
472
    uint32_t cmdtype;
476
    uint32_t cmdtype;
473
    uint32_t direction;
477
    uint32_t direction;
Line 483... Line 487...
483
        cmdtype = SDCI_CMD_CMD_TYPE_ADTC;
487
        cmdtype = SDCI_CMD_CMD_TYPE_ADTC;
484
        responsetype = SDCI_CMD_RES_TYPE_R1;
488
        responsetype = SDCI_CMD_RES_TYPE_R1;
485
        direction = MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_READ;
489
        direction = MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_READ;
486
        invalidate_dcache();
490
        invalidate_dcache();
487
    }
491
    }
488
    SDCI_DMASIZE = 0x200;
492
    SDCI_DMASIZE = blksize;
489
    SDCI_DMAADDR = buf;
493
    SDCI_DMAADDR = buf;
490
    SDCI_DMACOUNT = count;
494
    SDCI_DMACOUNT = count;
491
    SDCI_DCTRL = SDCI_DCTRL_TXFIFORST | SDCI_DCTRL_RXFIFORST;
495
    SDCI_DCTRL = SDCI_DCTRL_TXFIFORST | SDCI_DCTRL_RXFIFORST;
492
    PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_BLOCK)
496
    PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_BLOCK)
493
                           | SDCI_CMD_CMD_TYPE_ADTC | cmdtype | responsetype
497
                           | SDCI_CMD_CMD_TYPE_ADTC | cmdtype | responsetype
Line 517... Line 521...
517
    {
521
    {
518
        memset(ceata_taskfile, 0, 16);
522
        memset(ceata_taskfile, 0, 16);
519
        ceata_taskfile[0xf] = 0xec;
523
        ceata_taskfile[0xf] = 0xec;
520
        PASS_RC(ceata_wait_idle(), 2, 0);
524
        PASS_RC(ceata_wait_idle(), 2, 0);
521
        PASS_RC(ceata_write_multiple_register(0, ceata_taskfile, 16), 2, 1);
525
        PASS_RC(ceata_write_multiple_register(0, ceata_taskfile, 16), 2, 1);
522
        PASS_RC(ceata_rw_multiple_block(false, buf, 1, CEATA_COMMAND_TIMEOUT), 2, 2);
526
        PASS_RC(ceata_rw_multiple_block(false, buf, 1, 256, CEATA_COMMAND_TIMEOUT), 2, 2);
523
    }
527
    }
524
    else
528
    else
525
    {
529
    {
526
        PASS_RC(ata_wait_for_not_bsy(10000000), 1, 0);
530
        PASS_RC(ata_wait_for_not_bsy(10000000), 2, 0);
527
        ata_write_cbr(&ATA_PIO_DVR, 0);
531
        ata_write_cbr(&ATA_PIO_DVR, 0);
528
        ata_write_cbr(&ATA_PIO_CSD, 0xec);
532
        ata_write_cbr(&ATA_PIO_CSD, 0xec);
529
        PASS_RC(ata_wait_for_start_of_transfer(10000000), 1, 1);
533
        PASS_RC(ata_wait_for_start_of_transfer(10000000), 2, 1);
530
        for (i = 0; i < 0x100; i++) buf[i] = ata_read_cbr(&ATA_PIO_DTR);
534
        for (i = 0; i < 0x100; i++) buf[i] = ata_read_cbr(&ATA_PIO_DTR);
-
 
535
        PASS_RC(ata_wait_for_end_of_transfer(100000), 2, 2);
531
    }
536
    }
532
    return 0;
537
    return 0;
533
}
538
}
534
 
539
 
535
void ata_set_active(void)
540
void ata_set_active(void)
Line 739... Line 744...
739
        ceata_taskfile[0xc] = sector >> 5;
744
        ceata_taskfile[0xc] = sector >> 5;
740
        ceata_taskfile[0xd] = sector >> 13;
745
        ceata_taskfile[0xd] = sector >> 13;
741
        ceata_taskfile[0xf] = write ? 0x35 : 0x25;
746
        ceata_taskfile[0xf] = write ? 0x35 : 0x25;
742
        PASS_RC(ceata_wait_idle(), 2, 0);
747
        PASS_RC(ceata_wait_idle(), 2, 0);
743
        PASS_RC(ceata_write_multiple_register(0, ceata_taskfile, 16), 2, 1);
748
        PASS_RC(ceata_write_multiple_register(0, ceata_taskfile, 16), 2, 1);
744
        PASS_RC(ceata_rw_multiple_block(write, buffer, cnt << 3, CEATA_COMMAND_TIMEOUT), 2, 2);
749
        PASS_RC(ceata_rw_multiple_block(write, buffer, cnt << 3, 512, CEATA_COMMAND_TIMEOUT), 2, 2);
745
    }
750
    }
746
    else
751
    else
747
    {
752
    {
748
        PASS_RC(ata_wait_for_rdy(100000), 2, 0);
753
        PASS_RC(ata_wait_for_rdy(100000), 2, 0);
749
        ata_write_cbr(&ATA_PIO_DVR, 0);
754
        ata_write_cbr(&ATA_PIO_DVR, 0);
Line 1010... Line 1015...
1010
    }
1015
    }
1011
    ata_set_active();
1016
    ata_set_active();
1012
    mutex_unlock(&ata_mutex);
1017
    mutex_unlock(&ata_mutex);
1013
    return rc;
1018
    return rc;
1014
}
1019
}
-
 
1020
 
-
 
1021
int ata_read_taskfile(struct ata_raw_cmd_t* cmd)
-
 
1022
{
-
 
1023
    mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
-
 
1024
    if (!ata_powered) PASS_RC(ata_power_up(), 1, 0);
-
 
1025
    ata_set_active();
-
 
1026
    cmd->result_valid = false;
-
 
1027
    if (ceata)
-
 
1028
    {
-
 
1029
        PASS_RC_MTX(ceata_read_multiple_register(0, ceata_taskfile, 16), 1, 1, &ata_mutex);
-
 
1030
        cmd->feature = ceata_taskfile[0x9];
-
 
1031
        cmd->count = ceata_taskfile[0xa];
-
 
1032
        cmd->lba_low = ceata_taskfile[0xb];
-
 
1033
        cmd->lba_mid = ceata_taskfile[0xc];
-
 
1034
        cmd->lba_high = ceata_taskfile[0xd];
-
 
1035
        cmd->device = ceata_taskfile[0xe];
-
 
1036
        cmd->command = ceata_taskfile[0xf];
-
 
1037
        if (cmd->lba48)
-
 
1038
        {
-
 
1039
            cmd->feature |= ceata_taskfile[0x1] << 8;
-
 
1040
            cmd->count |= ceata_taskfile[0x2] << 8;
-
 
1041
            cmd->lba_low |= ceata_taskfile[0x3] << 8;
-
 
1042
            cmd->lba_mid |= ceata_taskfile[0x4] << 8;
-
 
1043
            cmd->lba_high |= ceata_taskfile[0x5] << 8;
-
 
1044
        }
-
 
1045
    }
-
 
1046
    else
-
 
1047
    {
-
 
1048
        cmd->feature = ata_read_cbr(&ATA_PIO_FED);
-
 
1049
        cmd->count = ata_read_cbr(&ATA_PIO_SCR);
-
 
1050
        cmd->lba_low = ata_read_cbr(&ATA_PIO_LLR);
-
 
1051
        cmd->lba_mid = ata_read_cbr(&ATA_PIO_LMR);
-
 
1052
        cmd->lba_high = ata_read_cbr(&ATA_PIO_LHR);
-
 
1053
        cmd->device = ata_read_cbr(&ATA_PIO_DVR);
-
 
1054
        cmd->command = ata_read_cbr(&ATA_PIO_CSD);
-
 
1055
        if (cmd->lba48)
-
 
1056
        {
-
 
1057
            ata_write_cbr(&ATA_PIO_DAD, BIT(7));
-
 
1058
            cmd->feature |= ata_read_cbr(&ATA_PIO_FED) << 8;
-
 
1059
            cmd->count |= ata_read_cbr(&ATA_PIO_SCR) << 8;
-
 
1060
            cmd->lba_low |= ata_read_cbr(&ATA_PIO_LLR) << 8;
-
 
1061
            cmd->lba_mid |= ata_read_cbr(&ATA_PIO_LMR) << 8;
-
 
1062
            cmd->lba_high |= ata_read_cbr(&ATA_PIO_LHR) << 8;
-
 
1063
            ata_write_cbr(&ATA_PIO_DAD, 0);
-
 
1064
        }
-
 
1065
    }
-
 
1066
    cmd->result_valid = true;
-
 
1067
    ata_set_active();
-
 
1068
    mutex_unlock(&ata_mutex);
-
 
1069
    return 0;
-
 
1070
}
-
 
1071
 
-
 
1072
int ata_raw_cmd(struct ata_raw_cmd_t* cmd)
-
 
1073
{
-
 
1074
    mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
-
 
1075
    if (!ata_powered) PASS_RC(ata_power_up(), 3, 0);
-
 
1076
    ata_set_active();
-
 
1077
    int rc = 0, rc2 = 0;
-
 
1078
    cmd->result_valid = false;
-
 
1079
    if (ceata)
-
 
1080
    {
-
 
1081
        memset(ceata_taskfile, 0, 16);
-
 
1082
        if (cmd->lba48)
-
 
1083
        {
-
 
1084
            ceata_taskfile[0x1] = cmd->feature >> 8;
-
 
1085
            ceata_taskfile[0x2] = cmd->count >> 8;
-
 
1086
            ceata_taskfile[0x3] = cmd->lba_low >> 8;
-
 
1087
            ceata_taskfile[0x4] = cmd->lba_mid >> 8;
-
 
1088
            ceata_taskfile[0x5] = cmd->lba_high >> 8;
-
 
1089
        }
-
 
1090
        ceata_taskfile[0x9] = cmd->feature & 0xff;
-
 
1091
        ceata_taskfile[0xa] = cmd->count & 0xff;
-
 
1092
        ceata_taskfile[0xb] = cmd->lba_low & 0xff;
-
 
1093
        ceata_taskfile[0xc] = cmd->lba_mid & 0xff;
-
 
1094
        ceata_taskfile[0xd] = cmd->lba_high & 0xff;
-
 
1095
        ceata_taskfile[0xe] = cmd->device;
-
 
1096
        ceata_taskfile[0xf] = cmd->command;
-
 
1097
        PASS_RC_MTX(ceata_wait_idle(), 3, 1, &ata_mutex);
-
 
1098
        PASS_RC_MTX(ceata_write_multiple_register(0, ceata_taskfile, 16), 3, 2, &ata_mutex);
-
 
1099
        if (cmd->transfer)
-
 
1100
            rc = ceata_rw_multiple_block(cmd->send, cmd->buffer, cmd->size, cmd->blksize, CEATA_COMMAND_TIMEOUT);
-
 
1101
        else rc = ceata_wait_idle();
-
 
1102
        if (IS_ERR(rc)) rc = ERR_RC((rc << 3) | 3);
-
 
1103
        rc2 = ata_read_taskfile(cmd);
-
 
1104
        if (IS_ERR(rc2) && !IS_ERR(rc)) rc = ERR_RC((rc2 << 3) | 4);
-
 
1105
    }
-
 
1106
    else
-
 
1107
    {
-
 
1108
        PASS_RC_MTX(ata_wait_for_rdy(100000), 3, 1, &ata_mutex);
-
 
1109
        ata_write_cbr(&ATA_PIO_DVR, 0);
-
 
1110
        if (cmd->lba48)
-
 
1111
        {
-
 
1112
            ata_write_cbr(&ATA_PIO_FED, cmd->feature >> 8);
-
 
1113
            ata_write_cbr(&ATA_PIO_SCR, cmd->count >> 8);
-
 
1114
            ata_write_cbr(&ATA_PIO_LLR, cmd->lba_low >> 8);
-
 
1115
            ata_write_cbr(&ATA_PIO_LMR, cmd->lba_mid >> 8);
-
 
1116
            ata_write_cbr(&ATA_PIO_LHR, cmd->lba_high >> 8);
-
 
1117
        }
-
 
1118
        ata_write_cbr(&ATA_PIO_FED, cmd->feature & 0xff);
-
 
1119
        ata_write_cbr(&ATA_PIO_SCR, cmd->count & 0xff);
-
 
1120
        ata_write_cbr(&ATA_PIO_LLR, cmd->lba_low & 0xff);
-
 
1121
        ata_write_cbr(&ATA_PIO_LMR, cmd->lba_mid & 0xff);
-
 
1122
        ata_write_cbr(&ATA_PIO_LHR, cmd->lba_high & 0xff);
-
 
1123
        ata_write_cbr(&ATA_PIO_DVR, cmd->device);
-
 
1124
        ata_write_cbr(&ATA_PIO_CSD, cmd->command);
-
 
1125
        sleep(cmd->delay);
-
 
1126
        if (cmd->transfer)
-
 
1127
        {
-
 
1128
            if (cmd->dma)
-
 
1129
            {
-
 
1130
                rc = ata_wait_for_start_of_transfer(500000);
-
 
1131
                if (IS_ERR(rc)) rc = ERR_RC((rc << 3) | 2);
-
 
1132
                else
-
 
1133
                {
-
 
1134
                    if (cmd->send)
-
 
1135
                    {
-
 
1136
                        clean_dcache();
-
 
1137
                        ATA_SBUF_START = cmd->buffer;
-
 
1138
                        ATA_SBUF_SIZE = cmd->size * cmd->blksize;
-
 
1139
                        ATA_CFG |= BIT(4);
-
 
1140
                    }
-
 
1141
                    else
-
 
1142
                    {
-
 
1143
                        invalidate_dcache();
-
 
1144
                        ATA_TBUF_START = cmd->buffer;
-
 
1145
                        ATA_TBUF_SIZE = cmd->size * cmd->blksize;
-
 
1146
                        ATA_CFG &= ~BIT(4);
-
 
1147
                    }
-
 
1148
                    ATA_XFR_NUM = cmd->blksize * cmd->size - 1;
-
 
1149
                    ATA_CFG |= ata_dma_flags;
-
 
1150
                    ATA_CFG &= ~(BIT(7) | BIT(8));
-
 
1151
                    wakeup_wait(&ata_wakeup, TIMEOUT_NONE);
-
 
1152
                    ATA_IRQ = BITRANGE(0, 4);
-
 
1153
                    ATA_IRQ_MASK = BIT(0);
-
 
1154
                    ATA_COMMAND = BIT(0);
-
 
1155
                    if (wakeup_wait(&ata_wakeup, 500000) == THREAD_TIMEOUT) rc = ERR_RC(3);
-
 
1156
                    ATA_COMMAND = BIT(1);
-
 
1157
                    ATA_CFG &= ~(BITRANGE(2, 3) | BIT(12));
-
 
1158
                }
-
 
1159
            }
-
 
1160
            else
-
 
1161
            {
-
 
1162
                ATA_CFG &= ~ata_dma_flags;
-
 
1163
                while (cmd->size--)
-
 
1164
                {
-
 
1165
                    rc = ata_wait_for_start_of_transfer(500000);
-
 
1166
                    if (IS_ERR(rc))
-
 
1167
                    {
-
 
1168
                        rc = ERR_RC((rc << 3) | 4);
-
 
1169
                        break;
-
 
1170
                    }
-
 
1171
                    int i;
-
 
1172
                    if (cmd->send)
-
 
1173
                        for (i = 0; i < (cmd->blksize >> 1); i++)
-
 
1174
                            ata_write_cbr(&ATA_PIO_DTR, ((uint16_t*)cmd->buffer)[i]);
-
 
1175
                    else
-
 
1176
                        for (i = 0; i < (cmd->blksize >> 1); i++)
-
 
1177
                            ((uint16_t*)cmd->buffer)[i] = ata_read_cbr(&ATA_PIO_DTR);
-
 
1178
                    cmd->buffer += cmd->blksize;
-
 
1179
                }
-
 
1180
            }
-
 
1181
            if (!IS_ERR(rc))
-
 
1182
            {
-
 
1183
                rc = ata_wait_for_end_of_transfer(100000);
-
 
1184
                if (IS_ERR(rc)) rc = ERR_RC((rc << 3) | 5);
-
 
1185
            }
-
 
1186
        }
-
 
1187
        else
-
 
1188
        {
-
 
1189
            rc = ata_wait_for_rdy(500000);
-
 
1190
            if (IS_ERR(rc)) rc = ERR_RC((rc << 3) | 6);
-
 
1191
        }
-
 
1192
        ata_read_taskfile(cmd);  // Cannot fail for PATA
-
 
1193
    }
-
 
1194
    ata_set_active();
-
 
1195
    mutex_unlock(&ata_mutex);
-
 
1196
    return rc;
-
 
1197
}
1015
 
1198
 
1016
int ata_read_sectors(IF_MD2(int drive,) unsigned long start, int incount,
1199
int ata_read_sectors(IF_MD2(int drive,) unsigned long start, int incount,
1017
                     void* inbuf)
1200
                     void* inbuf)
1018
{
1201
{
1019
    mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
1202
    mutex_lock(&ata_mutex, TIMEOUT_BLOCK);