WebSVN – freemyipod – Diff – /emcore/trunk/target/ipodclassic/storage_ata.c



#define CEATA_MMC_RCA 1
 
 
/** static, private data **/ 
static uint8_t ceata_taskfile[16] __attribute__((aligned(16)));
uint16_t ata_identify_data[0x100] __attribute__((aligned(16)));
bool ceata;
bool ata_lba48;
bool ata_dma;
uint64_t ata_total_sectors;
struct mutex ata_mutex;

    mmc_discard_irq();
    SDCI_DMASIZE = size;
    SDCI_DMACOUNT = 1;
    SDCI_DMAADDR = dest;
    SDCI_DCTRL = SDCI_DCTRL_TXFIFORST | SDCI_DCTRL_RXFIFORST;
    invalidate_dcache();
    PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_REG)
                           | SDCI_CMD_CMD_TYPE_ADTC | SDCI_CMD_RES_TYPE_R1
                           | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
                             MMC_CMD_CEATA_RW_MULTIPLE_REG_DIRECTION_READ
                           | MMC_CMD_CEATA_RW_MULTIPLE_REG_ADDRESS(addr & 0xfc)
                           | MMC_CMD_CEATA_RW_MULTIPLE_REG_COUNT(size & 0xfc),
                             NULL, CEATA_COMMAND_TIMEOUT), 2, 1);
    long startusec = USEC_TIMER;
    if (wakeup_wait(&mmc_wakeup, CEATA_COMMAND_TIMEOUT) == THREAD_TIMEOUT) RET_ERR(2);
 
    PASS_RC(mmc_dsta_check_data_success(), 2, 3);
    return 0;
}
 
int ceata_write_multiple_register(uint32_t addr, void* dest, uint32_t size)

    uint32_t responsetype;
    uint32_t cmdtype;
    uint32_t direction;
    if (write)
    {
 
        cmdtype = SDCI_CMD_CMD_TYPE_ADTC | SDCI_CMD_CMD_RD_WR;
        responsetype = SDCI_CMD_RES_TYPE_R1 | SDCI_CMD_RES_BUSY;
        direction = MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_WRITE;
    }
    else

    }
    SDCI_DMASIZE = 0x200;
    SDCI_DMAADDR = buf;
    SDCI_DMACOUNT = count;
    SDCI_DCTRL = SDCI_DCTRL_TXFIFORST | SDCI_DCTRL_RXFIFORST;
    invalidate_dcache();
    PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_BLOCK)
                           | SDCI_CMD_CMD_TYPE_ADTC | cmdtype | responsetype
                           | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
                             direction | MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_COUNT(count),
                             NULL, CEATA_COMMAND_TIMEOUT), 4, 0);

    if (wakeup_wait(&mmc_wakeup, timeout) == THREAD_TIMEOUT)
    {
        PASS_RC(ceata_cancel_command(), 4, 1);
        RET_ERR(2);
    }
 
    PASS_RC(mmc_dsta_check_data_success(), 4, 3);
    if (wakeup_wait(&mmc_comp_wakeup, timeout) == THREAD_TIMEOUT)
    {
        PASS_RC(ceata_cancel_command(), 4, 4);
        RET_ERR(4);

        memset(ceata_taskfile, 0, 16);
        ceata_taskfile[0xf] = 0xec;
        PASS_RC(ceata_wait_idle(), 2, 0);
        PASS_RC(ceata_write_multiple_register(0, ceata_taskfile, 16), 2, 1);
        PASS_RC(ceata_rw_multiple_block(false, buf, 1, CEATA_COMMAND_TIMEOUT), 2, 2);
 
 
 
 
 
    }
    else
    {
        PASS_RC(ata_wait_for_not_bsy(10000000), 1, 0);
        ata_write_cbr(&ATA_PIO_DVR, 0);

Rev 629	Rev 636
Line 39...	Line 39...
39	`#define CEATA_MMC_RCA 1`	39	`#define CEATA_MMC_RCA 1`
40		40
41		41
42	`/ static, private data /`	42	`/ static, private data /`
43	`static uint8_t ceata_taskfile[16] __attribute__((aligned(16)));`	43	`static uint8_t ceata_taskfile[16] __attribute__((aligned(16)));`
44	`uint16_t ata_identify_data[0x100];`	44	`uint16_t ata_identify_data[0x100] __attribute__((aligned(16)));`
45	`bool ceata;`	45	`bool ceata;`
46	`bool ata_lba48;`	46	`bool ata_lba48;`
47	`bool ata_dma;`	47	`bool ata_dma;`
48	`uint64_t ata_total_sectors;`	48	`uint64_t ata_total_sectors;`
49	`struct mutex ata_mutex;`	49	`struct mutex ata_mutex;`
Line 341...	Line 341...
341	`mmc_discard_irq();`	341	`mmc_discard_irq();`
342	`SDCI_DMASIZE = size;`	342	`SDCI_DMASIZE = size;`
343	`SDCI_DMACOUNT = 1;`	343	`SDCI_DMACOUNT = 1;`
344	`SDCI_DMAADDR = dest;`	344	`SDCI_DMAADDR = dest;`
345	`SDCI_DCTRL = SDCI_DCTRL_TXFIFORST \| SDCI_DCTRL_RXFIFORST;`	345	`SDCI_DCTRL = SDCI_DCTRL_TXFIFORST \| SDCI_DCTRL_RXFIFORST;`
-		346	`invalidate_dcache();`
346	`PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_REG)`	347	`PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_REG)`
347	`\| SDCI_CMD_CMD_TYPE_ADTC \| SDCI_CMD_RES_TYPE_R1`	348	`\| SDCI_CMD_CMD_TYPE_ADTC \| SDCI_CMD_RES_TYPE_R1`
348	`\| SDCI_CMD_RES_SIZE_48 \| SDCI_CMD_NCR_NID_NCR,`	349	`\| SDCI_CMD_RES_SIZE_48 \| SDCI_CMD_NCR_NID_NCR,`
349	`MMC_CMD_CEATA_RW_MULTIPLE_REG_DIRECTION_READ`	350	`MMC_CMD_CEATA_RW_MULTIPLE_REG_DIRECTION_READ`
350	`\| MMC_CMD_CEATA_RW_MULTIPLE_REG_ADDRESS(addr & 0xfc)`	351	`\| MMC_CMD_CEATA_RW_MULTIPLE_REG_ADDRESS(addr & 0xfc)`
351	`\| MMC_CMD_CEATA_RW_MULTIPLE_REG_COUNT(size & 0xfc),`	352	`\| MMC_CMD_CEATA_RW_MULTIPLE_REG_COUNT(size & 0xfc),`
352	`NULL, CEATA_COMMAND_TIMEOUT), 2, 1);`	353	`NULL, CEATA_COMMAND_TIMEOUT), 2, 1);`
353	`long startusec = USEC_TIMER;`	354	`long startusec = USEC_TIMER;`
354	`if (wakeup_wait(&mmc_wakeup, CEATA_COMMAND_TIMEOUT) == THREAD_TIMEOUT) RET_ERR(2);`	355	`if (wakeup_wait(&mmc_wakeup, CEATA_COMMAND_TIMEOUT) == THREAD_TIMEOUT) RET_ERR(2);`
355	`invalidate_dcache();`	-
356	`PASS_RC(mmc_dsta_check_data_success(), 2, 3);`	356	`PASS_RC(mmc_dsta_check_data_success(), 2, 3);`
357	`return 0;`	357	`return 0;`
358	`}`	358	`}`
359		359
360	`int ceata_write_multiple_register(uint32_t addr, void* dest, uint32_t size)`	360	`int ceata_write_multiple_register(uint32_t addr, void* dest, uint32_t size)`
Line 470...	Line 470...
470	`uint32_t responsetype;`	470	`uint32_t responsetype;`
471	`uint32_t cmdtype;`	471	`uint32_t cmdtype;`
472	`uint32_t direction;`	472	`uint32_t direction;`
473	`if (write)`	473	`if (write)`
474	`{`	474	`{`
475	`clean_dcache();`	-
476	`cmdtype = SDCI_CMD_CMD_TYPE_ADTC \| SDCI_CMD_CMD_RD_WR;`	475	`cmdtype = SDCI_CMD_CMD_TYPE_ADTC \| SDCI_CMD_CMD_RD_WR;`
477	`responsetype = SDCI_CMD_RES_TYPE_R1 \| SDCI_CMD_RES_BUSY;`	476	`responsetype = SDCI_CMD_RES_TYPE_R1 \| SDCI_CMD_RES_BUSY;`
478	`direction = MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_WRITE;`	477	`direction = MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_WRITE;`
479	`}`	478	`}`
480	`else`	479	`else`
Line 485...	Line 484...
485	`}`	484	`}`
486	`SDCI_DMASIZE = 0x200;`	485	`SDCI_DMASIZE = 0x200;`
487	`SDCI_DMAADDR = buf;`	486	`SDCI_DMAADDR = buf;`
488	`SDCI_DMACOUNT = count;`	487	`SDCI_DMACOUNT = count;`
489	`SDCI_DCTRL = SDCI_DCTRL_TXFIFORST \| SDCI_DCTRL_RXFIFORST;`	488	`SDCI_DCTRL = SDCI_DCTRL_TXFIFORST \| SDCI_DCTRL_RXFIFORST;`
-		489	`invalidate_dcache();`
490	`PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_BLOCK)`	490	`PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_BLOCK)`
491	`\| SDCI_CMD_CMD_TYPE_ADTC \| cmdtype \| responsetype`	491	`\| SDCI_CMD_CMD_TYPE_ADTC \| cmdtype \| responsetype`
492	`\| SDCI_CMD_RES_SIZE_48 \| SDCI_CMD_NCR_NID_NCR,`	492	`\| SDCI_CMD_RES_SIZE_48 \| SDCI_CMD_NCR_NID_NCR,`
493	`direction \| MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_COUNT(count),`	493	`direction \| MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_COUNT(count),`
494	`NULL, CEATA_COMMAND_TIMEOUT), 4, 0);`	494	`NULL, CEATA_COMMAND_TIMEOUT), 4, 0);`
Line 496...	Line 496...
496	`if (wakeup_wait(&mmc_wakeup, timeout) == THREAD_TIMEOUT)`	496	`if (wakeup_wait(&mmc_wakeup, timeout) == THREAD_TIMEOUT)`
497	`{`	497	`{`
498	`PASS_RC(ceata_cancel_command(), 4, 1);`	498	`PASS_RC(ceata_cancel_command(), 4, 1);`
499	`RET_ERR(2);`	499	`RET_ERR(2);`
500	`}`	500	`}`
501	`if (!write) invalidate_dcache();`	-
502	`PASS_RC(mmc_dsta_check_data_success(), 4, 3);`	501	`PASS_RC(mmc_dsta_check_data_success(), 4, 3);`
503	`if (wakeup_wait(&mmc_comp_wakeup, timeout) == THREAD_TIMEOUT)`	502	`if (wakeup_wait(&mmc_comp_wakeup, timeout) == THREAD_TIMEOUT)`
504	`{`	503	`{`
505	`PASS_RC(ceata_cancel_command(), 4, 4);`	504	`PASS_RC(ceata_cancel_command(), 4, 4);`
506	`RET_ERR(4);`	505	`RET_ERR(4);`
Line 517...	Line 516...
517	`memset(ceata_taskfile, 0, 16);`	516	`memset(ceata_taskfile, 0, 16);`
518	`ceata_taskfile[0xf] = 0xec;`	517	`ceata_taskfile[0xf] = 0xec;`
519	`PASS_RC(ceata_wait_idle(), 2, 0);`	518	`PASS_RC(ceata_wait_idle(), 2, 0);`
520	`PASS_RC(ceata_write_multiple_register(0, ceata_taskfile, 16), 2, 1);`	519	`PASS_RC(ceata_write_multiple_register(0, ceata_taskfile, 16), 2, 1);`
521	`PASS_RC(ceata_rw_multiple_block(false, buf, 1, CEATA_COMMAND_TIMEOUT), 2, 2);`	520	`PASS_RC(ceata_rw_multiple_block(false, buf, 1, CEATA_COMMAND_TIMEOUT), 2, 2);`
522	`for (i = 0; i < 0x100; i++)`	-
523	`{`	-
524	`uint16_t word = buf[i];`	-
525	`buf[i] = (word >> 8) \| (word << 8);`	-
526	`}`	-
527	`}`	521	`}`
528	`else`	522	`else`
529	`{`	523	`{`
530	`PASS_RC(ata_wait_for_not_bsy(10000000), 1, 0);`	524	`PASS_RC(ata_wait_for_not_bsy(10000000), 1, 0);`
531	`ata_write_cbr(&ATA_PIO_DVR, 0);`	525	`ata_write_cbr(&ATA_PIO_DVR, 0);`

Subversion Repositories freemyipod

(root)/emcore/trunk/target/ipodclassic/storage_ata.c @ 636 – Rev 629 → 636