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Line 3... Line 3...
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OUTPUT_ARCH(arm)
3
OUTPUT_ARCH(arm)
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STARTUP(build/ipodclassic/target/ipodclassic/crt0.o)
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STARTUP(build/ipodclassic/target/ipodclassic/crt0.o)
5
 
5
 
6
MEMORY
6
MEMORY
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{
7
{
8
    INIT : ORIGIN = 0x08000000, LENGTH = 0x01eff000
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    INIT : ORIGIN = 0x08000000, LENGTH = 0x03f80000
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    INITBSS : ORIGIN = 0x0be00000, LENGTH = 0x000ff000
-
 
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    INITSTACK : ORIGIN = 0x0beff000, LENGTH = 0x00001000
-
 
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    SRAM : ORIGIN = 0x22000000, LENGTH = 0x0003c000
9
    SRAM : ORIGIN = 0x22000000, LENGTH = 0x0003c000
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    SDRAM : ORIGIN = 0x0bf00000, LENGTH = 0x00100000
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    SDRAM : ORIGIN = 0x0bf80000, LENGTH = 0x00080000
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}
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}
14
 
12
 
15
SECTIONS
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SECTIONS
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{
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{
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    .init :
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    .inithead :
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    {
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    {
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        _initstart = .;
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        _initheadstart = .;
-
 
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        _poolstart = .;
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	*(.inithead*)
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	*(.inithead*)
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        *(.initcode*)
-
 
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        *(.initrodata*)
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        *(.initdata*)
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        . = ALIGN(0x4);
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        . = ALIGN(0x4);
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        _initend = .;
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        _initheadend = .;
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    } > INIT
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    } > INIT
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23
 
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    .sram :
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    .sram :
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    {
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    {
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        _sramstart = .;
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        _sramstart = .;
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    _sramsource = LOADADDR(.sram);
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    _sramsource = LOADADDR(.sram);
40
 
36
 
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    .sdram :
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    .sdram :
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    {
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    {
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        _sdramstart = .;
39
        _sdramstart = .;
-
 
40
        _poolend = .;
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        *(.text*)
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        *(.text*)
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        *(.glue_7)
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        *(.glue_7)
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        *(.glue_7t)
43
        *(.glue_7t)
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        . = ALIGN(0x4);
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        . = ALIGN(0x4);
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        *(.rodata*)
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        *(.rodata*)
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        . = ALIGN(0x4);
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        . = ALIGN(0x4);
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        _sdramend = .;
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        _sdramend = .;
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    } > SDRAM AT> INIT
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    } > SDRAM AT> INIT
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    _sdramsource = LOADADDR(.sdram);
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    _sdramsource = LOADADDR(.sdram);
55
 
52
 
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    .initbss (NOLOAD) :
53
    .init :
57
    {
54
    {
58
        _initbssstart = .;
55
        _initstart = .;
-
 
56
        *(.initcode*)
-
 
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        *(.initrodata*)
-
 
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        *(.initdata*)
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        *(.initbss*)
59
        *(.inittail*)
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        . = ALIGN(0x4);
60
        . = ALIGN(0x4);
61
        _initstackstart = .;
-
 
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        . += 0x400;
-
 
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        _initstackend = .;
-
 
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        _initbssend = .;
61
        _initend = .;
65
    } > INITBSS
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    } > INIT
66
 
63
 
67
    .ibss (NOLOAD) :
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    .ibss (NOLOAD) :
68
    {
65
    {
69
        _ibssstart = .;
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        _ibssstart = .;
70
        *(.ibss*)
67
        *(.ibss*)
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        _irqstackend = .;
71
        _irqstackend = .;
75
        _abortstackstart = .;
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        _abortstackstart = .;
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        . += 0x400;
73
        . += 0x400;
77
        _abortstackend = .;
74
        _abortstackend = .;
78
        *(.stack*)
75
        *(.stack*)
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        . = ALIGN(0x4);
79
        _ibssend = .;
77
        _ibssend = .;
80
    } > SRAM
78
    } > SRAM
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79
 
82
    .bss (NOLOAD) :
80
    .bss (NOLOAD) :
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    {
81
    {
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        *(COMMON)
84
        *(COMMON)
87
        . = ALIGN(0x4);
85
        . = ALIGN(0x4);
88
        _bssend = .;
86
        _bssend = .;
89
    } > SDRAM
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    } > SDRAM
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88
 
91
    .initstack (NOLOAD) :
-
 
92
    {
-
 
93
        _loadspaceend = .;
-
 
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        *(.initstack*)
-
 
95
        *(COMMON)
-
 
96
        . = ALIGN(0x4);
-
 
97
    } > INITSTACK
-
 
98
 
-
 
99
    /DISCARD/ :
89
    /DISCARD/ :
100
    {
90
    {
101
        *(.eh_frame)
91
        *(.eh_frame)
102
    }
92
    }
103
 
93