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/*** OTG PHY CONTROL REGISTERS ***/
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/*** OTG PHY CONTROL REGISTERS ***/
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#define OPHYPWR     (*((uint32_t volatile*)(PHYBASE + 0x000)))
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#define OPHYPWR     (*((uint32_t volatile*)(PHYBASE + 0x000)))
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#define OPHYCLK     (*((uint32_t volatile*)(PHYBASE + 0x004)))
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#define OPHYCLK     (*((uint32_t volatile*)(PHYBASE + 0x004)))
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#define ORSTCON     (*((uint32_t volatile*)(PHYBASE + 0x008)))
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#define ORSTCON     (*((uint32_t volatile*)(PHYBASE + 0x008)))
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#define OPHYUNK3    (*((uint32_t volatile*)(PHYBASE + 0x018)))
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#define OPHYUNK1    (*((uint32_t volatile*)(PHYBASE + 0x01c)))
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#define OPHYUNK1    (*((uint32_t volatile*)(PHYBASE + 0x01c)))
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#define OPHYUNK2    (*((uint32_t volatile*)(PHYBASE + 0x044)))
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#define OPHYUNK2    (*((uint32_t volatile*)(PHYBASE + 0x044)))
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/*** OTG LINK CORE REGISTERS ***/
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/*** OTG LINK CORE REGISTERS ***/
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/* Core Global Registers */
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/* Core Global Registers */