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Rev 265 Rev 274
Line 141... Line 141...
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    OPHYUNK2 = 0xE3F;
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    OPHYUNK2 = 0xE3F;
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    OPHYCLK = SYNOPSYSOTG_CLOCK;
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    OPHYCLK = SYNOPSYSOTG_CLOCK;
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    ORSTCON = 1;  /* PHY: Assert Software Reset */
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    ORSTCON = 1;  /* PHY: Assert Software Reset */
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    udelay(10);
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    udelay(10);
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    ORSTCON = 0;  /* PHY: Deassert Software Reset */
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    ORSTCON = 0;  /* PHY: Deassert Software Reset */
- 
 
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    OPHYUNK3 = 0x600;
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    GRSTCTL = 1;  /* OTG: Assert Software Reset */
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    GRSTCTL = 1;  /* OTG: Assert Software Reset */
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    while (GRSTCTL & 1);  /* Wait for OTG to ack reset */
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    while (GRSTCTL & 1);  /* Wait for OTG to ack reset */
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    while (!(GRSTCTL & 0x80000000));  /* Wait for OTG AHB master idle */
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    while (!(GRSTCTL & 0x80000000));  /* Wait for OTG AHB master idle */
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