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15 theseven 1 
//
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//
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//    Copyright 2010 TheSeven
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//
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//
427 farthen 6 
//    This file is part of emCORE.
15 theseven 7 
//
427 farthen 8 
//    emCORE is free software: you can redistribute it and/or
15 theseven 9 
//    modify it under the terms of the GNU General Public License as
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//    published by the Free Software Foundation, either version 2 of the
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//    License, or (at your option) any later version.
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//
427 farthen 13 
//    emCORE is distributed in the hope that it will be useful,
15 theseven 14 
//    but WITHOUT ANY WARRANTY; without even the implied warranty of
15 
//    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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//    See the GNU General Public License for more details.
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//
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//    You should have received a copy of the GNU General Public License along
427 farthen 19 
//    with emCORE.  If not, see <http://www.gnu.org/licenses/>.
15 theseven 20 
//
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//
22 
 
23 
 
24 
#ifndef __SYNOPSYSOTG_H__
25 
#define __SYNOPSYSOTG_H__
26 
 
27 
 
28 
#include "global.h"
29 
 
30 
 
31 
#ifdef TARGET_ipodnano2g
111 theseven 32 
#include "target/ipodnano2g/s5l8701.h"
15 theseven 33 
#endif
265 theseven 34 
#if defined(TARGET_ipodnano3g) || defined(TARGET_ipodclassic)
35 
#include "target/ipodnano3g/s5l8702.h"
36 
#endif
710 theseven 37 
#if defined(TARGET_ipodnano4g) || defined(TARGET_ipodtouch2g)
111 theseven 38 
#include "target/ipodnano4g/s5l8720.h"
85 theseven 39 
#endif
15 theseven 40 
 
41 
 
42 
/*** OTG PHY CONTROL REGISTERS ***/
265 theseven 43 
#define OPHYPWR     (*((uint32_t volatile*)(PHYBASE + 0x000)))
44 
#define OPHYCLK     (*((uint32_t volatile*)(PHYBASE + 0x004)))
45 
#define ORSTCON     (*((uint32_t volatile*)(PHYBASE + 0x008)))
274 theseven 46 
#define OPHYUNK3    (*((uint32_t volatile*)(PHYBASE + 0x018)))
265 theseven 47 
#define OPHYUNK1    (*((uint32_t volatile*)(PHYBASE + 0x01c)))
48 
#define OPHYUNK2    (*((uint32_t volatile*)(PHYBASE + 0x044)))
15 theseven 49 
 
50 
/*** OTG LINK CORE REGISTERS ***/
51 
/* Core Global Registers */
265 theseven 52 
#define GOTGCTL     (*((uint32_t volatile*)(OTGBASE + 0x000)))
53 
#define GOTGINT     (*((uint32_t volatile*)(OTGBASE + 0x004)))
54 
#define GAHBCFG     (*((uint32_t volatile*)(OTGBASE + 0x008)))
55 
#define GUSBCFG     (*((uint32_t volatile*)(OTGBASE + 0x00C)))
56 
#define GRSTCTL     (*((uint32_t volatile*)(OTGBASE + 0x010)))
57 
#define GINTSTS     (*((uint32_t volatile*)(OTGBASE + 0x014)))
58 
#define GINTMSK     (*((uint32_t volatile*)(OTGBASE + 0x018)))
59 
#define GRXSTSR     (*((uint32_t volatile*)(OTGBASE + 0x01C)))
60 
#define GRXSTSP     (*((uint32_t volatile*)(OTGBASE + 0x020)))
61 
#define GRXFSIZ     (*((uint32_t volatile*)(OTGBASE + 0x024)))
62 
#define GNPTXFSIZ   (*((uint32_t volatile*)(OTGBASE + 0x028)))
63 
#define GNPTXSTS    (*((uint32_t volatile*)(OTGBASE + 0x02C)))
64 
#define HPTXFSIZ    (*((uint32_t volatile*)(OTGBASE + 0x100)))
65 
#define DPTXFSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x100 + 4 * (x))))
66 
#define DPTXFSIZ1   (*((uint32_t volatile*)(OTGBASE + 0x104)))
67 
#define DPTXFSIZ2   (*((uint32_t volatile*)(OTGBASE + 0x108)))
68 
#define DPTXFSIZ3   (*((uint32_t volatile*)(OTGBASE + 0x10C)))
69 
#define DPTXFSIZ4   (*((uint32_t volatile*)(OTGBASE + 0x110)))
70 
#define DPTXFSIZ5   (*((uint32_t volatile*)(OTGBASE + 0x114)))
71 
#define DPTXFSIZ6   (*((uint32_t volatile*)(OTGBASE + 0x118)))
72 
#define DPTXFSIZ7   (*((uint32_t volatile*)(OTGBASE + 0x11C)))
73 
#define DPTXFSIZ8   (*((uint32_t volatile*)(OTGBASE + 0x120)))
74 
#define DPTXFSIZ9   (*((uint32_t volatile*)(OTGBASE + 0x124)))
75 
#define DPTXFSIZ10  (*((uint32_t volatile*)(OTGBASE + 0x128)))
76 
#define DPTXFSIZ11  (*((uint32_t volatile*)(OTGBASE + 0x12C)))
77 
#define DPTXFSIZ12  (*((uint32_t volatile*)(OTGBASE + 0x130)))
78 
#define DPTXFSIZ13  (*((uint32_t volatile*)(OTGBASE + 0x134)))
79 
#define DPTXFSIZ14  (*((uint32_t volatile*)(OTGBASE + 0x138)))
80 
#define DPTXFSIZ15  (*((uint32_t volatile*)(OTGBASE + 0x13C)))
15 theseven 81 
 
82 
/*** HOST MODE REGISTERS ***/
83 
/* Host Global Registers */
265 theseven 84 
#define HCFG        (*((uint32_t volatile*)(OTGBASE + 0x400)))
85 
#define HFIR        (*((uint32_t volatile*)(OTGBASE + 0x404)))
86 
#define HFNUM       (*((uint32_t volatile*)(OTGBASE + 0x408)))
87 
#define HPTXSTS     (*((uint32_t volatile*)(OTGBASE + 0x410)))
88 
#define HAINT       (*((uint32_t volatile*)(OTGBASE + 0x414)))
89 
#define HAINTMSK    (*((uint32_t volatile*)(OTGBASE + 0x418)))
15 theseven 90 
 
91 
/* Host Port Control and Status Registers */
265 theseven 92 
#define HPRT        (*((uint32_t volatile*)(OTGBASE + 0x440)))
15 theseven 93 
 
94 
/* Host Channel-Specific Registers */
265 theseven 95 
#define HCCHAR(x)   (*((uint32_t volatile*)(OTGBASE + 0x500 + 0x20 * (x))))
96 
#define HCSPLT(x)   (*((uint32_t volatile*)(OTGBASE + 0x504 + 0x20 * (x))))
97 
#define HCINT(x)    (*((uint32_t volatile*)(OTGBASE + 0x508 + 0x20 * (x))))
98 
#define HCINTMSK(x) (*((uint32_t volatile*)(OTGBASE + 0x50C + 0x20 * (x))))
99 
#define HCTSIZ(x)   (*((uint32_t volatile*)(OTGBASE + 0x510 + 0x20 * (x))))
100 
#define HCDMA(x)    (*((uint32_t volatile*)(OTGBASE + 0x514 + 0x20 * (x))))
101 
#define HCCHAR0     (*((uint32_t volatile*)(OTGBASE + 0x500)))
102 
#define HCSPLT0     (*((uint32_t volatile*)(OTGBASE + 0x504)))
103 
#define HCINT0      (*((uint32_t volatile*)(OTGBASE + 0x508)))
104 
#define HCINTMSK0   (*((uint32_t volatile*)(OTGBASE + 0x50C)))
105 
#define HCTSIZ0     (*((uint32_t volatile*)(OTGBASE + 0x510)))
106 
#define HCDMA0      (*((uint32_t volatile*)(OTGBASE + 0x514)))
107 
#define HCCHAR1     (*((uint32_t volatile*)(OTGBASE + 0x520)))
108 
#define HCSPLT1     (*((uint32_t volatile*)(OTGBASE + 0x524)))
109 
#define HCINT1      (*((uint32_t volatile*)(OTGBASE + 0x528)))
110 
#define HCINTMSK1   (*((uint32_t volatile*)(OTGBASE + 0x52C)))
111 
#define HCTSIZ1     (*((uint32_t volatile*)(OTGBASE + 0x530)))
112 
#define HCDMA1      (*((uint32_t volatile*)(OTGBASE + 0x534)))
113 
#define HCCHAR2     (*((uint32_t volatile*)(OTGBASE + 0x540)))
114 
#define HCSPLT2     (*((uint32_t volatile*)(OTGBASE + 0x544)))
115 
#define HCINT2      (*((uint32_t volatile*)(OTGBASE + 0x548)))
116 
#define HCINTMSK2   (*((uint32_t volatile*)(OTGBASE + 0x54C)))
117 
#define HCTSIZ2     (*((uint32_t volatile*)(OTGBASE + 0x550)))
118 
#define HCDMA2      (*((uint32_t volatile*)(OTGBASE + 0x554)))
119 
#define HCCHAR3     (*((uint32_t volatile*)(OTGBASE + 0x560)))
120 
#define HCSPLT3     (*((uint32_t volatile*)(OTGBASE + 0x564)))
121 
#define HCINT3      (*((uint32_t volatile*)(OTGBASE + 0x568)))
122 
#define HCINTMSK3   (*((uint32_t volatile*)(OTGBASE + 0x56C)))
123 
#define HCTSIZ3     (*((uint32_t volatile*)(OTGBASE + 0x570)))
124 
#define HCDMA3      (*((uint32_t volatile*)(OTGBASE + 0x574)))
125 
#define HCCHAR4     (*((uint32_t volatile*)(OTGBASE + 0x580)))
126 
#define HCSPLT4     (*((uint32_t volatile*)(OTGBASE + 0x584)))
127 
#define HCINT4      (*((uint32_t volatile*)(OTGBASE + 0x588)))
128 
#define HCINTMSK4   (*((uint32_t volatile*)(OTGBASE + 0x58C)))
129 
#define HCTSIZ4     (*((uint32_t volatile*)(OTGBASE + 0x590)))
130 
#define HCDMA4      (*((uint32_t volatile*)(OTGBASE + 0x594)))
131 
#define HCCHAR5     (*((uint32_t volatile*)(OTGBASE + 0x5A0)))
132 
#define HCSPLT5     (*((uint32_t volatile*)(OTGBASE + 0x5A4)))
133 
#define HCINT5      (*((uint32_t volatile*)(OTGBASE + 0x5A8)))
134 
#define HCINTMSK5   (*((uint32_t volatile*)(OTGBASE + 0x5AC)))
135 
#define HCTSIZ5     (*((uint32_t volatile*)(OTGBASE + 0x5B0)))
136 
#define HCDMA5      (*((uint32_t volatile*)(OTGBASE + 0x5B4)))
137 
#define HCCHAR6     (*((uint32_t volatile*)(OTGBASE + 0x5C0)))
138 
#define HCSPLT6     (*((uint32_t volatile*)(OTGBASE + 0x5C4)))
139 
#define HCINT6      (*((uint32_t volatile*)(OTGBASE + 0x5C8)))
140 
#define HCINTMSK6   (*((uint32_t volatile*)(OTGBASE + 0x5CC)))
141 
#define HCTSIZ6     (*((uint32_t volatile*)(OTGBASE + 0x5D0)))
142 
#define HCDMA6      (*((uint32_t volatile*)(OTGBASE + 0x5D4)))
143 
#define HCCHAR7     (*((uint32_t volatile*)(OTGBASE + 0x5E0)))
144 
#define HCSPLT7     (*((uint32_t volatile*)(OTGBASE + 0x5E4)))
145 
#define HCINT7      (*((uint32_t volatile*)(OTGBASE + 0x5E8)))
146 
#define HCINTMSK7   (*((uint32_t volatile*)(OTGBASE + 0x5EC)))
147 
#define HCTSIZ7     (*((uint32_t volatile*)(OTGBASE + 0x5F0)))
148 
#define HCDMA7      (*((uint32_t volatile*)(OTGBASE + 0x5F4)))
149 
#define HCCHAR8     (*((uint32_t volatile*)(OTGBASE + 0x600)))
150 
#define HCSPLT8     (*((uint32_t volatile*)(OTGBASE + 0x604)))
151 
#define HCINT8      (*((uint32_t volatile*)(OTGBASE + 0x608)))
152 
#define HCINTMSK8   (*((uint32_t volatile*)(OTGBASE + 0x60C)))
153 
#define HCTSIZ8     (*((uint32_t volatile*)(OTGBASE + 0x610)))
154 
#define HCDMA8      (*((uint32_t volatile*)(OTGBASE + 0x614)))
155 
#define HCCHAR9     (*((uint32_t volatile*)(OTGBASE + 0x620)))
156 
#define HCSPLT9     (*((uint32_t volatile*)(OTGBASE + 0x624)))
157 
#define HCINT9      (*((uint32_t volatile*)(OTGBASE + 0x628)))
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#define HCINTMSK9   (*((uint32_t volatile*)(OTGBASE + 0x62C)))
159 
#define HCTSIZ9     (*((uint32_t volatile*)(OTGBASE + 0x630)))
160 
#define HCDMA9      (*((uint32_t volatile*)(OTGBASE + 0x634)))
161 
#define HCCHAR10    (*((uint32_t volatile*)(OTGBASE + 0x640)))
162 
#define HCSPLT10    (*((uint32_t volatile*)(OTGBASE + 0x644)))
163 
#define HCINT10     (*((uint32_t volatile*)(OTGBASE + 0x648)))
164 
#define HCINTMSK10  (*((uint32_t volatile*)(OTGBASE + 0x64C)))
165 
#define HCTSIZ10    (*((uint32_t volatile*)(OTGBASE + 0x650)))
166 
#define HCDMA10     (*((uint32_t volatile*)(OTGBASE + 0x654)))
167 
#define HCCHAR11    (*((uint32_t volatile*)(OTGBASE + 0x660)))
168 
#define HCSPLT11    (*((uint32_t volatile*)(OTGBASE + 0x664)))
169 
#define HCINT11     (*((uint32_t volatile*)(OTGBASE + 0x668)))
170 
#define HCINTMSK11  (*((uint32_t volatile*)(OTGBASE + 0x66C)))
171 
#define HCTSIZ11    (*((uint32_t volatile*)(OTGBASE + 0x670)))
172 
#define HCDMA11     (*((uint32_t volatile*)(OTGBASE + 0x674)))
173 
#define HCCHAR12    (*((uint32_t volatile*)(OTGBASE + 0x680)))
174 
#define HCSPLT12    (*((uint32_t volatile*)(OTGBASE + 0x684)))
175 
#define HCINT12     (*((uint32_t volatile*)(OTGBASE + 0x688)))
176 
#define HCINTMSK12  (*((uint32_t volatile*)(OTGBASE + 0x68C)))
177 
#define HCTSIZ12    (*((uint32_t volatile*)(OTGBASE + 0x690)))
178 
#define HCDMA12     (*((uint32_t volatile*)(OTGBASE + 0x694)))
179 
#define HCCHAR13    (*((uint32_t volatile*)(OTGBASE + 0x6A0)))
180 
#define HCSPLT13    (*((uint32_t volatile*)(OTGBASE + 0x6A4)))
181 
#define HCINT13     (*((uint32_t volatile*)(OTGBASE + 0x6A8)))
182 
#define HCINTMSK13  (*((uint32_t volatile*)(OTGBASE + 0x6AC)))
183 
#define HCTSIZ13    (*((uint32_t volatile*)(OTGBASE + 0x6B0)))
184 
#define HCDMA13     (*((uint32_t volatile*)(OTGBASE + 0x6B4)))
185 
#define HCCHAR14    (*((uint32_t volatile*)(OTGBASE + 0x6C0)))
186 
#define HCSPLT14    (*((uint32_t volatile*)(OTGBASE + 0x6C4)))
187 
#define HCINT14     (*((uint32_t volatile*)(OTGBASE + 0x6C8)))
188 
#define HCINTMSK14  (*((uint32_t volatile*)(OTGBASE + 0x6CC)))
189 
#define HCTSIZ14    (*((uint32_t volatile*)(OTGBASE + 0x6D0)))
190 
#define HCDMA14     (*((uint32_t volatile*)(OTGBASE + 0x6D4)))
191 
#define HCCHAR15    (*((uint32_t volatile*)(OTGBASE + 0x6E0)))
192 
#define HCSPLT15    (*((uint32_t volatile*)(OTGBASE + 0x6E4)))
193 
#define HCINT15     (*((uint32_t volatile*)(OTGBASE + 0x6E8)))
194 
#define HCINTMSK15  (*((uint32_t volatile*)(OTGBASE + 0x6EC)))
195 
#define HCTSIZ15    (*((uint32_t volatile*)(OTGBASE + 0x6F0)))
196 
#define HCDMA15     (*((uint32_t volatile*)(OTGBASE + 0x6F4)))
15 theseven 197 
 
198 
/*** DEVICE MODE REGISTERS ***/
199 
/* Device Global Registers */
265 theseven 200 
#define DCFG        (*((uint32_t volatile*)(OTGBASE + 0x800)))
201 
#define DCTL        (*((uint32_t volatile*)(OTGBASE + 0x804)))
202 
#define DSTS        (*((uint32_t volatile*)(OTGBASE + 0x808)))
203 
#define DIEPMSK     (*((uint32_t volatile*)(OTGBASE + 0x810)))
204 
#define DOEPMSK     (*((uint32_t volatile*)(OTGBASE + 0x814)))
205 
#define DAINT       (*((uint32_t volatile*)(OTGBASE + 0x818)))
206 
#define DAINTMSK    (*((uint32_t volatile*)(OTGBASE + 0x81C)))
207 
#define DTKNQR1     (*((uint32_t volatile*)(OTGBASE + 0x820)))
208 
#define DTKNQR2     (*((uint32_t volatile*)(OTGBASE + 0x824)))
209 
#define DVBUSDIS    (*((uint32_t volatile*)(OTGBASE + 0x828)))
210 
#define DVBUSPULSE  (*((uint32_t volatile*)(OTGBASE + 0x82C)))
211 
#define DTKNQR3     (*((uint32_t volatile*)(OTGBASE + 0x830)))
212 
#define DTKNQR4     (*((uint32_t volatile*)(OTGBASE + 0x834)))
15 theseven 213 
 
214 
/* Device Logical IN Endpoint-Specific Registers */
265 theseven 215 
#define DIEPCTL(x)  (*((uint32_t volatile*)(OTGBASE + 0x900 + 0x20 * (x))))
216 
#define DIEPINT(x)  (*((uint32_t volatile*)(OTGBASE + 0x908 + 0x20 * (x))))
217 
#define DIEPTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x910 + 0x20 * (x))))
218 
#define DIEPDMA(x)  (*((const void* volatile*)(OTGBASE + 0x914 + 0x20 * (x))))
219 
#define DIEPCTL0    (*((uint32_t volatile*)(OTGBASE + 0x900)))
220 
#define DIEPINT0    (*((uint32_t volatile*)(OTGBASE + 0x908)))
221 
#define DIEPTSIZ0   (*((uint32_t volatile*)(OTGBASE + 0x910)))
222 
#define DIEPDMA0    (*((const void* volatile*)(OTGBASE + 0x914)))
223 
#define DIEPCTL1    (*((uint32_t volatile*)(OTGBASE + 0x920)))
224 
#define DIEPINT1    (*((uint32_t volatile*)(OTGBASE + 0x928)))
225 
#define DIEPTSIZ1   (*((uint32_t volatile*)(OTGBASE + 0x930)))
226 
#define DIEPDMA1    (*((const void* volatile*)(OTGBASE + 0x934)))
227 
#define DIEPCTL2    (*((uint32_t volatile*)(OTGBASE + 0x940)))
228 
#define DIEPINT2    (*((uint32_t volatile*)(OTGBASE + 0x948)))
229 
#define DIEPTSIZ2   (*((uint32_t volatile*)(OTGBASE + 0x950)))
230 
#define DIEPDMA2    (*((const void* volatile*)(OTGBASE + 0x954)))
231 
#define DIEPCTL3    (*((uint32_t volatile*)(OTGBASE + 0x960)))
232 
#define DIEPINT3    (*((uint32_t volatile*)(OTGBASE + 0x968)))
233 
#define DIEPTSIZ3   (*((uint32_t volatile*)(OTGBASE + 0x970)))
234 
#define DIEPDMA3    (*((const void* volatile*)(OTGBASE + 0x974)))
235 
#define DIEPCTL4    (*((uint32_t volatile*)(OTGBASE + 0x980)))
236 
#define DIEPINT4    (*((uint32_t volatile*)(OTGBASE + 0x988)))
237 
#define DIEPTSIZ4   (*((uint32_t volatile*)(OTGBASE + 0x990)))
238 
#define DIEPDMA4    (*((const void* volatile*)(OTGBASE + 0x994)))
239 
#define DIEPCTL5    (*((uint32_t volatile*)(OTGBASE + 0x9A0)))
240 
#define DIEPINT5    (*((uint32_t volatile*)(OTGBASE + 0x9A8)))
241 
#define DIEPTSIZ5   (*((uint32_t volatile*)(OTGBASE + 0x9B0)))
242 
#define DIEPDMA5    (*((const void* volatile*)(OTGBASE + 0x9B4)))
243 
#define DIEPCTL6    (*((uint32_t volatile*)(OTGBASE + 0x9C0)))
244 
#define DIEPINT6    (*((uint32_t volatile*)(OTGBASE + 0x9C8)))
245 
#define DIEPTSIZ6   (*((uint32_t volatile*)(OTGBASE + 0x9D0)))
246 
#define DIEPDMA6    (*((const void* volatile*)(OTGBASE + 0x9D4)))
247 
#define DIEPCTL7    (*((uint32_t volatile*)(OTGBASE + 0x9E0)))
248 
#define DIEPINT7    (*((uint32_t volatile*)(OTGBASE + 0x9E8)))
249 
#define DIEPTSIZ7   (*((uint32_t volatile*)(OTGBASE + 0x9F0)))
250 
#define DIEPDMA7    (*((const void* volatile*)(OTGBASE + 0x9F4)))
251 
#define DIEPCTL8    (*((uint32_t volatile*)(OTGBASE + 0xA00)))
252 
#define DIEPINT8    (*((uint32_t volatile*)(OTGBASE + 0xA08)))
253 
#define DIEPTSIZ8   (*((uint32_t volatile*)(OTGBASE + 0xA10)))
254 
#define DIEPDMA8    (*((const void* volatile*)(OTGBASE + 0xA14)))
255 
#define DIEPCTL9    (*((uint32_t volatile*)(OTGBASE + 0xA20)))
256 
#define DIEPINT9    (*((uint32_t volatile*)(OTGBASE + 0xA28)))
257 
#define DIEPTSIZ9   (*((uint32_t volatile*)(OTGBASE + 0xA30)))
258 
#define DIEPDMA9    (*((const void* volatile*)(OTGBASE + 0xA34)))
259 
#define DIEPCTL10   (*((uint32_t volatile*)(OTGBASE + 0xA40)))
260 
#define DIEPINT10   (*((uint32_t volatile*)(OTGBASE + 0xA48)))
261 
#define DIEPTSIZ10  (*((uint32_t volatile*)(OTGBASE + 0xA50)))
262 
#define DIEPDMA10   (*((const void* volatile*)(OTGBASE + 0xA54)))
263 
#define DIEPCTL11   (*((uint32_t volatile*)(OTGBASE + 0xA60)))
264 
#define DIEPINT11   (*((uint32_t volatile*)(OTGBASE + 0xA68)))
265 
#define DIEPTSIZ11  (*((uint32_t volatile*)(OTGBASE + 0xA70)))
266 
#define DIEPDMA11   (*((const void* volatile*)(OTGBASE + 0xA74)))
267 
#define DIEPCTL12   (*((uint32_t volatile*)(OTGBASE + 0xA80)))
268 
#define DIEPINT12   (*((uint32_t volatile*)(OTGBASE + 0xA88)))
269 
#define DIEPTSIZ12  (*((uint32_t volatile*)(OTGBASE + 0xA90)))
270 
#define DIEPDMA12   (*((const void* volatile*)(OTGBASE + 0xA94)))
271 
#define DIEPCTL13   (*((uint32_t volatile*)(OTGBASE + 0xAA0)))
272 
#define DIEPINT13   (*((uint32_t volatile*)(OTGBASE + 0xAA8)))
273 
#define DIEPTSIZ13  (*((uint32_t volatile*)(OTGBASE + 0xAB0)))
274 
#define DIEPDMA13   (*((const void* volatile*)(OTGBASE + 0xAB4)))
275 
#define DIEPCTL14   (*((uint32_t volatile*)(OTGBASE + 0xAC0)))
276 
#define DIEPINT14   (*((uint32_t volatile*)(OTGBASE + 0xAC8)))
277 
#define DIEPTSIZ14  (*((uint32_t volatile*)(OTGBASE + 0xAD0)))
278 
#define DIEPDMA14   (*((const void* volatile*)(OTGBASE + 0xAD4)))
279 
#define DIEPCTL15   (*((uint32_t volatile*)(OTGBASE + 0xAE0)))
280 
#define DIEPINT15   (*((uint32_t volatile*)(OTGBASE + 0xAE8)))
281 
#define DIEPTSIZ15  (*((uint32_t volatile*)(OTGBASE + 0xAF0)))
282 
#define DIEPDMA15   (*((const void* volatile*)(OTGBASE + 0xAF4)))
15 theseven 283 
 
284 
/* Device Logical OUT Endpoint-Specific Registers */
265 theseven 285 
#define DOEPCTL(x)  (*((uint32_t volatile*)(OTGBASE + 0xB00 + 0x20 * (x))))
286 
#define DOEPINT(x)  (*((uint32_t volatile*)(OTGBASE + 0xB08 + 0x20 * (x))))
287 
#define DOEPTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0xB10 + 0x20 * (x))))
288 
#define DOEPDMA(x)  (*((void* volatile*)(OTGBASE + 0xB14 + 0x20 * (x))))
289 
#define DOEPCTL0    (*((uint32_t volatile*)(OTGBASE + 0xB00)))
290 
#define DOEPINT0    (*((uint32_t volatile*)(OTGBASE + 0xB08)))
291 
#define DOEPTSIZ0   (*((uint32_t volatile*)(OTGBASE + 0xB10)))
292 
#define DOEPDMA0    (*((void* volatile*)(OTGBASE + 0xB14)))
293 
#define DOEPCTL1    (*((uint32_t volatile*)(OTGBASE + 0xB20)))
294 
#define DOEPINT1    (*((uint32_t volatile*)(OTGBASE + 0xB28)))
295 
#define DOEPTSIZ1   (*((uint32_t volatile*)(OTGBASE + 0xB30)))
296 
#define DOEPDMA1    (*((void* volatile*)(OTGBASE + 0xB34)))
297 
#define DOEPCTL2    (*((uint32_t volatile*)(OTGBASE + 0xB40)))
298 
#define DOEPINT2    (*((uint32_t volatile*)(OTGBASE + 0xB48)))
299 
#define DOEPTSIZ2   (*((uint32_t volatile*)(OTGBASE + 0xB50)))
300 
#define DOEPDMA2    (*((void* volatile*)(OTGBASE + 0xB54)))
301 
#define DOEPCTL3    (*((uint32_t volatile*)(OTGBASE + 0xB60)))
302 
#define DOEPINT3    (*((uint32_t volatile*)(OTGBASE + 0xB68)))
303 
#define DOEPTSIZ3   (*((uint32_t volatile*)(OTGBASE + 0xB70)))
304 
#define DOEPDMA3    (*((void* volatile*)(OTGBASE + 0xB74)))
305 
#define DOEPCTL4    (*((uint32_t volatile*)(OTGBASE + 0xB80)))
306 
#define DOEPINT4    (*((uint32_t volatile*)(OTGBASE + 0xB88)))
307 
#define DOEPTSIZ4   (*((uint32_t volatile*)(OTGBASE + 0xB90)))
308 
#define DOEPDMA4    (*((void* volatile*)(OTGBASE + 0xB94)))
309 
#define DOEPCTL5    (*((uint32_t volatile*)(OTGBASE + 0xBA0)))
310 
#define DOEPINT5    (*((uint32_t volatile*)(OTGBASE + 0xBA8)))
311 
#define DOEPTSIZ5   (*((uint32_t volatile*)(OTGBASE + 0xBB0)))
312 
#define DOEPDMA5    (*((void* volatile*)(OTGBASE + 0xBB4)))
313 
#define DOEPCTL6    (*((uint32_t volatile*)(OTGBASE + 0xBC0)))
314 
#define DOEPINT6    (*((uint32_t volatile*)(OTGBASE + 0xBC8)))
315 
#define DOEPTSIZ6   (*((uint32_t volatile*)(OTGBASE + 0xBD0)))
316 
#define DOEPDMA6    (*((void* volatile*)(OTGBASE + 0xBD4)))
317 
#define DOEPCTL7    (*((uint32_t volatile*)(OTGBASE + 0xBE0)))
318 
#define DOEPINT7    (*((uint32_t volatile*)(OTGBASE + 0xBE8)))
319 
#define DOEPTSIZ7   (*((uint32_t volatile*)(OTGBASE + 0xBF0)))
320 
#define DOEPDMA7    (*((void* volatile*)(OTGBASE + 0xBF4)))
321 
#define DOEPCTL8    (*((uint32_t volatile*)(OTGBASE + 0xC00)))
322 
#define DOEPINT8    (*((uint32_t volatile*)(OTGBASE + 0xC08)))
323 
#define DOEPTSIZ8   (*((uint32_t volatile*)(OTGBASE + 0xC10)))
324 
#define DOEPDMA8    (*((void* volatile*)(OTGBASE + 0xC14)))
325 
#define DOEPCTL9    (*((uint32_t volatile*)(OTGBASE + 0xC20)))
326 
#define DOEPINT9    (*((uint32_t volatile*)(OTGBASE + 0xC28)))
327 
#define DOEPTSIZ9   (*((uint32_t volatile*)(OTGBASE + 0xC30)))
328 
#define DOEPDMA9    (*((void* volatile*)(OTGBASE + 0xC34)))
329 
#define DOEPCTL10   (*((uint32_t volatile*)(OTGBASE + 0xC40)))
330 
#define DOEPINT10   (*((uint32_t volatile*)(OTGBASE + 0xC48)))
331 
#define DOEPTSIZ10  (*((uint32_t volatile*)(OTGBASE + 0xC50)))
332 
#define DOEPDMA10   (*((void* volatile*)(OTGBASE + 0xC54)))
333 
#define DOEPCTL11   (*((uint32_t volatile*)(OTGBASE + 0xC60)))
334 
#define DOEPINT11   (*((uint32_t volatile*)(OTGBASE + 0xC68)))
335 
#define DOEPTSIZ11  (*((uint32_t volatile*)(OTGBASE + 0xC70)))
336 
#define DOEPDMA11   (*((void* volatile*)(OTGBASE + 0xC74)))
337 
#define DOEPCTL12   (*((uint32_t volatile*)(OTGBASE + 0xC80)))
338 
#define DOEPINT12   (*((uint32_t volatile*)(OTGBASE + 0xC88)))
339 
#define DOEPTSIZ12  (*((uint32_t volatile*)(OTGBASE + 0xC90)))
340 
#define DOEPDMA12   (*((void* volatile*)(OTGBASE + 0xC94)))
341 
#define DOEPCTL13   (*((uint32_t volatile*)(OTGBASE + 0xCA0)))
342 
#define DOEPINT13   (*((uint32_t volatile*)(OTGBASE + 0xCA8)))
343 
#define DOEPTSIZ13  (*((uint32_t volatile*)(OTGBASE + 0xCB0)))
344 
#define DOEPDMA13   (*((void* volatile*)(OTGBASE + 0xCB4)))
345 
#define DOEPCTL14   (*((uint32_t volatile*)(OTGBASE + 0xCC0)))
346 
#define DOEPINT14   (*((uint32_t volatile*)(OTGBASE + 0xCC8)))
347 
#define DOEPTSIZ14  (*((uint32_t volatile*)(OTGBASE + 0xCD0)))
348 
#define DOEPDMA14   (*((void* volatile*)(OTGBASE + 0xCD4)))
349 
#define DOEPCTL15   (*((uint32_t volatile*)(OTGBASE + 0xCE0)))
350 
#define DOEPINT15   (*((uint32_t volatile*)(OTGBASE + 0xCE8)))
351 
#define DOEPTSIZ15  (*((uint32_t volatile*)(OTGBASE + 0xCF0)))
352 
#define DOEPDMA15   (*((void* volatile*)(OTGBASE + 0xCF4)))
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354 
/* Power and Clock Gating Register */
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#define PCGCCTL     (*((uint32_t volatile*)(OTGBASE + 0xE00)))
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357 
 
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#endif