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//
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// Copyright 2010 TheSeven
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//
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//
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// This file is part of emCORE.
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//
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// emCORE is free software: you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as
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// published by the Free Software Foundation, either version 2 of the
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// License, or (at your option) any later version.
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//
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// emCORE is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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// See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with emCORE. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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#ifndef __S5L8702_H__
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#define __S5L8702_H__
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#include "global.h"
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/////SYSCON/////
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#define PWRCON(i) (*((uint32_t volatile*)(0x3C500000 \
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+ ((i) == 4 ? 0x6C : \
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((i) == 3 ? 0x68 : \
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((i) == 2 ? 0x58 : \
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((i) == 1 ? 0x4C : \
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0x48)))))))
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/////TIMER/////
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#define TACON (*((uint32_t volatile*)(0x3C700000)))
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#define TACMD (*((uint32_t volatile*)(0x3C700004)))
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#define TADATA0 (*((uint32_t volatile*)(0x3C700008)))
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#define TADATA1 (*((uint32_t volatile*)(0x3C70000C)))
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#define TAPRE (*((uint32_t volatile*)(0x3C700010)))
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#define TACNT (*((uint32_t volatile*)(0x3C700014)))
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#define TBCON (*((uint32_t volatile*)(0x3C700020)))
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#define TBCMD (*((uint32_t volatile*)(0x3C700024)))
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#define TBDATA0 (*((uint32_t volatile*)(0x3C700028)))
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#define TBDATA1 (*((uint32_t volatile*)(0x3C70002C)))
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#define TBPRE (*((uint32_t volatile*)(0x3C700030)))
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#define TBCNT (*((uint32_t volatile*)(0x3C700034)))
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#define TCCON (*((uint32_t volatile*)(0x3C700040)))
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#define TCCMD (*((uint32_t volatile*)(0x3C700044)))
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#define TCDATA0 (*((uint32_t volatile*)(0x3C700048)))
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#define TCDATA1 (*((uint32_t volatile*)(0x3C70004C)))
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#define TCPRE (*((uint32_t volatile*)(0x3C700050)))
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#define TCCNT (*((uint32_t volatile*)(0x3C700054)))
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#define TDCON (*((uint32_t volatile*)(0x3C700060)))
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#define TDCMD (*((uint32_t volatile*)(0x3C700064)))
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#define TDDATA0 (*((uint32_t volatile*)(0x3C700068)))
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#define TDDATA1 (*((uint32_t volatile*)(0x3C70006C)))
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#define TDPRE (*((uint32_t volatile*)(0x3C700070)))
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#define TDCNT (*((uint32_t volatile*)(0x3C700074)))
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#define TECON (*((uint32_t volatile*)(0x3C7000A0)))
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#define TECMD (*((uint32_t volatile*)(0x3C7000A4)))
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#define TEDATA0 (*((uint32_t volatile*)(0x3C7000A8)))
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#define TEDATA1 (*((uint32_t volatile*)(0x3C7000AC)))
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#define TEPRE (*((uint32_t volatile*)(0x3C7000B0)))
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#define TECNT (*((uint32_t volatile*)(0x3C7000B4)))
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#define TFCON (*((uint32_t volatile*)(0x3C7000C0)))
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#define TFCMD (*((uint32_t volatile*)(0x3C7000C4)))
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#define TFDATA0 (*((uint32_t volatile*)(0x3C7000C8)))
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#define TFDATA1 (*((uint32_t volatile*)(0x3C7000CC)))
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#define TFPRE (*((uint32_t volatile*)(0x3C7000D0)))
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#define TFCNT (*((uint32_t volatile*)(0x3C7000D4)))
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#define TGCON (*((uint32_t volatile*)(0x3C7000E0)))
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#define TGCMD (*((uint32_t volatile*)(0x3C7000E4)))
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#define TGDATA0 (*((uint32_t volatile*)(0x3C7000E8)))
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#define TGDATA1 (*((uint32_t volatile*)(0x3C7000EC)))
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#define TGPRE (*((uint32_t volatile*)(0x3C7000F0)))
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#define TGCNT (*((uint32_t volatile*)(0x3C7000F4)))
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#define THCON (*((uint32_t volatile*)(0x3C700100)))
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#define THCMD (*((uint32_t volatile*)(0x3C700104)))
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#define THDATA0 (*((uint32_t volatile*)(0x3C700108)))
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#define THDATA1 (*((uint32_t volatile*)(0x3C70010C)))
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#define THPRE (*((uint32_t volatile*)(0x3C700110)))
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#define THCNT (*((uint32_t volatile*)(0x3C700114)))
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/////USB/////
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#define OTGBASE 0x38400000
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#define PHYBASE 0x3C400000
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#define SYNOPSYSOTG_CLOCK 0
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#define SYNOPSYSOTG_AHBCFG 0x2B
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/////I2C/////
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#define IICCON(bus) (*((uint32_t volatile*)(0x3C600000 + 0x300000 * (bus))))
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#define IICSTAT(bus) (*((uint32_t volatile*)(0x3C600004 + 0x300000 * (bus))))
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#define IICADD(bus) (*((uint32_t volatile*)(0x3C600008 + 0x300000 * (bus))))
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#define IICDS(bus) (*((uint32_t volatile*)(0x3C60000C + 0x300000 * (bus))))
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#define IIC10(bus) (*((uint32_t volatile*)(0x3C600010 + 0x300000 * (bus))))
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/////INTERRUPT CONTROLLERS/////
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#define VICIRQSTATUS(v) (*((uint32_t volatile*)(0x38E00000 + 0x1000 * (v))))
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#define VICFIQSTATUS(v) (*((uint32_t volatile*)(0x38E00004 + 0x1000 * (v))))
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#define VICRAWINTR(v) (*((uint32_t volatile*)(0x38E00008 + 0x1000 * (v))))
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#define VICINTSELECT(v) (*((uint32_t volatile*)(0x38E0000C + 0x1000 * (v))))
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#define VICINTENABLE(v) (*((uint32_t volatile*)(0x38E00010 + 0x1000 * (v))))
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#define VICINTENCLEAR(v) (*((uint32_t volatile*)(0x38E00014 + 0x1000 * (v))))
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#define VICSOFTINT(v) (*((uint32_t volatile*)(0x38E00018 + 0x1000 * (v))))
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#define VICSOFTINTCLEAR(v) (*((uint32_t volatile*)(0x38E0001C + 0x1000 * (v))))
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#define VICPROTECTION(v) (*((uint32_t volatile*)(0x38E00020 + 0x1000 * (v))))
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#define VICSWPRIORITYMASK(v) (*((uint32_t volatile*)(0x38E00024 + 0x1000 * (v))))
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#define VICPRIORITYDAISY(v) (*((uint32_t volatile*)(0x38E00028 + 0x1000 * (v))))
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#define VICVECTADDR(v, i) (*((uint32_t volatile*)(0x38E00100 + 0x1000 * (v) + 4 * (i))))
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#define VICVECTPRIORITY(v, i) (*((uint32_t volatile*)(0x38E00200 + 0x1000 * (v) + 4 * (i))))
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#define VICADDRESS(v) (*((const void* volatile*)(0x38E00F00 + 0x1000 * (v))))
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#define VIC0IRQSTATUS (*((uint32_t volatile*)(0x38E00000)))
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#define VIC0FIQSTATUS (*((uint32_t volatile*)(0x38E00004)))
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#define VIC0RAWINTR (*((uint32_t volatile*)(0x38E00008)))
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#define VIC0INTSELECT (*((uint32_t volatile*)(0x38E0000C)))
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#define VIC0INTENABLE (*((uint32_t volatile*)(0x38E00010)))
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#define VIC0INTENCLEAR (*((uint32_t volatile*)(0x38E00014)))
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#define VIC0SOFTINT (*((uint32_t volatile*)(0x38E00018)))
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#define VIC0SOFTINTCLEAR (*((uint32_t volatile*)(0x38E0001C)))
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#define VIC0PROTECTION (*((uint32_t volatile*)(0x38E00020)))
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#define VIC0SWPRIORITYMASK (*((uint32_t volatile*)(0x38E00024)))
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#define VIC0PRIORITYDAISY (*((uint32_t volatile*)(0x38E00028)))
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#define VIC0VECTADDR(i) (*((const void* volatile*)(0x38E00100 + 4 * (i))))
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#define VIC0VECTADDR0 (*((const void* volatile*)(0x38E00100)))
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#define VIC0VECTADDR1 (*((const void* volatile*)(0x38E00104)))
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#define VIC0VECTADDR2 (*((const void* volatile*)(0x38E00108)))
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#define VIC0VECTADDR3 (*((const void* volatile*)(0x38E0010C)))
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#define VIC0VECTADDR4 (*((const void* volatile*)(0x38E00110)))
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#define VIC0VECTADDR5 (*((const void* volatile*)(0x38E00114)))
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#define VIC0VECTADDR6 (*((const void* volatile*)(0x38E00118)))
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#define VIC0VECTADDR7 (*((const void* volatile*)(0x38E0011C)))
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#define VIC0VECTADDR8 (*((const void* volatile*)(0x38E00120)))
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#define VIC0VECTADDR9 (*((const void* volatile*)(0x38E00124)))
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#define VIC0VECTADDR10 (*((const void* volatile*)(0x38E00128)))
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#define VIC0VECTADDR11 (*((const void* volatile*)(0x38E0012C)))
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#define VIC0VECTADDR12 (*((const void* volatile*)(0x38E00130)))
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#define VIC0VECTADDR13 (*((const void* volatile*)(0x38E00134)))
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#define VIC0VECTADDR14 (*((const void* volatile*)(0x38E00138)))
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#define VIC0VECTADDR15 (*((const void* volatile*)(0x38E0013C)))
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#define VIC0VECTADDR16 (*((const void* volatile*)(0x38E00140)))
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#define VIC0VECTADDR17 (*((const void* volatile*)(0x38E00144)))
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#define VIC0VECTADDR18 (*((const void* volatile*)(0x38E00148)))
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#define VIC0VECTADDR19 (*((const void* volatile*)(0x38E0014C)))
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#define VIC0VECTADDR20 (*((const void* volatile*)(0x38E00150)))
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#define VIC0VECTADDR21 (*((const void* volatile*)(0x38E00154)))
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#define VIC0VECTADDR22 (*((const void* volatile*)(0x38E00158)))
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#define VIC0VECTADDR23 (*((const void* volatile*)(0x38E0015C)))
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#define VIC0VECTADDR24 (*((const void* volatile*)(0x38E00160)))
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#define VIC0VECTADDR25 (*((const void* volatile*)(0x38E00164)))
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#define VIC0VECTADDR26 (*((const void* volatile*)(0x38E00168)))
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#define VIC0VECTADDR27 (*((const void* volatile*)(0x38E0016C)))
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#define VIC0VECTADDR28 (*((const void* volatile*)(0x38E00170)))
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#define VIC0VECTADDR29 (*((const void* volatile*)(0x38E00174)))
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#define VIC0VECTADDR30 (*((const void* volatile*)(0x38E00178)))
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#define VIC0VECTADDR31 (*((const void* volatile*)(0x38E0017C)))
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#define VIC0VECTPRIORITY(i) (*((uint32_t volatile*)(0x38E00200 + 4 * (i))))
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#define VIC0VECTPRIORITY0 (*((uint32_t volatile*)(0x38E00200)))
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#define VIC0VECTPRIORITY1 (*((uint32_t volatile*)(0x38E00204)))
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#define VIC0VECTPRIORITY2 (*((uint32_t volatile*)(0x38E00208)))
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#define VIC0VECTPRIORITY3 (*((uint32_t volatile*)(0x38E0020C)))
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#define VIC0VECTPRIORITY4 (*((uint32_t volatile*)(0x38E00210)))
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#define VIC0VECTPRIORITY5 (*((uint32_t volatile*)(0x38E00214)))
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#define VIC0VECTPRIORITY6 (*((uint32_t volatile*)(0x38E00218)))
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#define VIC0VECTPRIORITY7 (*((uint32_t volatile*)(0x38E0021C)))
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#define VIC0VECTPRIORITY8 (*((uint32_t volatile*)(0x38E00220)))
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#define VIC0VECTPRIORITY9 (*((uint32_t volatile*)(0x38E00224)))
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#define VIC0VECTPRIORITY10 (*((uint32_t volatile*)(0x38E00228)))
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#define VIC0VECTPRIORITY11 (*((uint32_t volatile*)(0x38E0022C)))
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#define VIC0VECTPRIORITY12 (*((uint32_t volatile*)(0x38E00230)))
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#define VIC0VECTPRIORITY13 (*((uint32_t volatile*)(0x38E00234)))
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#define VIC0VECTPRIORITY14 (*((uint32_t volatile*)(0x38E00238)))
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#define VIC0VECTPRIORITY15 (*((uint32_t volatile*)(0x38E0023C)))
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#define VIC0VECTPRIORITY16 (*((uint32_t volatile*)(0x38E00240)))
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#define VIC0VECTPRIORITY17 (*((uint32_t volatile*)(0x38E00244)))
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#define VIC0VECTPRIORITY18 (*((uint32_t volatile*)(0x38E00248)))
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#define VIC0VECTPRIORITY19 (*((uint32_t volatile*)(0x38E0024C)))
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#define VIC0VECTPRIORITY20 (*((uint32_t volatile*)(0x38E00250)))
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#define VIC0VECTPRIORITY21 (*((uint32_t volatile*)(0x38E00254)))
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#define VIC0VECTPRIORITY22 (*((uint32_t volatile*)(0x38E00258)))
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#define VIC0VECTPRIORITY23 (*((uint32_t volatile*)(0x38E0025C)))
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#define VIC0VECTPRIORITY24 (*((uint32_t volatile*)(0x38E00260)))
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#define VIC0VECTPRIORITY25 (*((uint32_t volatile*)(0x38E00264)))
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#define VIC0VECTPRIORITY26 (*((uint32_t volatile*)(0x38E00268)))
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#define VIC0VECTPRIORITY27 (*((uint32_t volatile*)(0x38E0026C)))
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#define VIC0VECTPRIORITY28 (*((uint32_t volatile*)(0x38E00270)))
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#define VIC0VECTPRIORITY29 (*((uint32_t volatile*)(0x38E00274)))
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#define VIC0VECTPRIORITY30 (*((uint32_t volatile*)(0x38E00278)))
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#define VIC0VECTPRIORITY31 (*((uint32_t volatile*)(0x38E0027C)))
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#define VIC0ADDRESS (*((void* volatile*)(0x38E00F00)))
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#define VIC1IRQSTATUS (*((uint32_t volatile*)(0x38E01000)))
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#define VIC1FIQSTATUS (*((uint32_t volatile*)(0x38E01004)))
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#define VIC1RAWINTR (*((uint32_t volatile*)(0x38E01008)))
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#define VIC1INTSELECT (*((uint32_t volatile*)(0x38E0100C)))
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#define VIC1INTENABLE (*((uint32_t volatile*)(0x38E01010)))
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#define VIC1INTENCLEAR (*((uint32_t volatile*)(0x38E01014)))
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#define VIC1SOFTINT (*((uint32_t volatile*)(0x38E01018)))
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#define VIC1SOFTINTCLEAR (*((uint32_t volatile*)(0x38E0101C)))
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#define VIC1PROTECTION (*((uint32_t volatile*)(0x38E01020)))
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#define VIC1SWPRIORITYMASK (*((uint32_t volatile*)(0x38E01024)))
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#define VIC1PRIORITYDAISY (*((uint32_t volatile*)(0x38E01028)))
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#define VIC1VECTADDR(i) (*((const void* volatile*)(0x38E01100 + 4 * (i))))
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#define VIC1VECTADDR0 (*((const void* volatile*)(0x38E01100)))
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#define VIC1VECTADDR1 (*((const void* volatile*)(0x38E01104)))
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#define VIC1VECTADDR2 (*((const void* volatile*)(0x38E01108)))
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#define VIC1VECTADDR3 (*((const void* volatile*)(0x38E0110C)))
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#define VIC1VECTADDR4 (*((const void* volatile*)(0x38E01110)))
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#define VIC1VECTADDR5 (*((const void* volatile*)(0x38E01114)))
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#define VIC1VECTADDR6 (*((const void* volatile*)(0x38E01118)))
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#define VIC1VECTADDR7 (*((const void* volatile*)(0x38E0111C)))
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#define VIC1VECTADDR8 (*((const void* volatile*)(0x38E01120)))
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#define VIC1VECTADDR9 (*((const void* volatile*)(0x38E01124)))
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#define VIC1VECTADDR10 (*((const void* volatile*)(0x38E01128)))
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#define VIC1VECTADDR11 (*((const void* volatile*)(0x38E0112C)))
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#define VIC1VECTADDR12 (*((const void* volatile*)(0x38E01130)))
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#define VIC1VECTADDR13 (*((const void* volatile*)(0x38E01134)))
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#define VIC1VECTADDR14 (*((const void* volatile*)(0x38E01138)))
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#define VIC1VECTADDR15 (*((const void* volatile*)(0x38E0113C)))
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#define VIC1VECTADDR16 (*((const void* volatile*)(0x38E01140)))
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#define VIC1VECTADDR17 (*((const void* volatile*)(0x38E01144)))
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#define VIC1VECTADDR18 (*((const void* volatile*)(0x38E01148)))
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229 |
#define VIC1VECTADDR19 (*((const void* volatile*)(0x38E0114C)))
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230 |
#define VIC1VECTADDR20 (*((const void* volatile*)(0x38E01150)))
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231 |
#define VIC1VECTADDR21 (*((const void* volatile*)(0x38E01154)))
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232 |
#define VIC1VECTADDR22 (*((const void* volatile*)(0x38E01158)))
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233 |
#define VIC1VECTADDR23 (*((const void* volatile*)(0x38E0115C)))
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234 |
#define VIC1VECTADDR24 (*((const void* volatile*)(0x38E01160)))
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235 |
#define VIC1VECTADDR25 (*((const void* volatile*)(0x38E01164)))
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236 |
#define VIC1VECTADDR26 (*((const void* volatile*)(0x38E01168)))
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237 |
#define VIC1VECTADDR27 (*((const void* volatile*)(0x38E0116C)))
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238 |
#define VIC1VECTADDR28 (*((const void* volatile*)(0x38E01170)))
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239 |
#define VIC1VECTADDR29 (*((const void* volatile*)(0x38E01174)))
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240 |
#define VIC1VECTADDR30 (*((const void* volatile*)(0x38E01178)))
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241 |
#define VIC1VECTADDR31 (*((const void* volatile*)(0x38E0117C)))
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242 |
#define VIC1VECTPRIORITY(i) (*((uint32_t volatile*)(0x38E01200 + 4 * (i))))
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243 |
#define VIC1VECTPRIORITY0 (*((uint32_t volatile*)(0x38E01200)))
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244 |
#define VIC1VECTPRIORITY1 (*((uint32_t volatile*)(0x38E01204)))
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245 |
#define VIC1VECTPRIORITY2 (*((uint32_t volatile*)(0x38E01208)))
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246 |
#define VIC1VECTPRIORITY3 (*((uint32_t volatile*)(0x38E0120C)))
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247 |
#define VIC1VECTPRIORITY4 (*((uint32_t volatile*)(0x38E01210)))
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248 |
#define VIC1VECTPRIORITY5 (*((uint32_t volatile*)(0x38E01214)))
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249 |
#define VIC1VECTPRIORITY6 (*((uint32_t volatile*)(0x38E01218)))
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250 |
#define VIC1VECTPRIORITY7 (*((uint32_t volatile*)(0x38E0121C)))
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251 |
#define VIC1VECTPRIORITY8 (*((uint32_t volatile*)(0x38E01220)))
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252 |
#define VIC1VECTPRIORITY9 (*((uint32_t volatile*)(0x38E01224)))
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253 |
#define VIC1VECTPRIORITY10 (*((uint32_t volatile*)(0x38E01228)))
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254 |
#define VIC1VECTPRIORITY11 (*((uint32_t volatile*)(0x38E0122C)))
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255 |
#define VIC1VECTPRIORITY12 (*((uint32_t volatile*)(0x38E01230)))
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256 |
#define VIC1VECTPRIORITY13 (*((uint32_t volatile*)(0x38E01234)))
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257 |
#define VIC1VECTPRIORITY14 (*((uint32_t volatile*)(0x38E01238)))
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258 |
#define VIC1VECTPRIORITY15 (*((uint32_t volatile*)(0x38E0123C)))
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259 |
#define VIC1VECTPRIORITY16 (*((uint32_t volatile*)(0x38E01240)))
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260 |
#define VIC1VECTPRIORITY17 (*((uint32_t volatile*)(0x38E01244)))
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261 |
#define VIC1VECTPRIORITY18 (*((uint32_t volatile*)(0x38E01248)))
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262 |
#define VIC1VECTPRIORITY19 (*((uint32_t volatile*)(0x38E0124C)))
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263 |
#define VIC1VECTPRIORITY20 (*((uint32_t volatile*)(0x38E01250)))
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264 |
#define VIC1VECTPRIORITY21 (*((uint32_t volatile*)(0x38E01254)))
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265 |
#define VIC1VECTPRIORITY22 (*((uint32_t volatile*)(0x38E01258)))
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266 |
#define VIC1VECTPRIORITY23 (*((uint32_t volatile*)(0x38E0125C)))
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267 |
#define VIC1VECTPRIORITY24 (*((uint32_t volatile*)(0x38E01260)))
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268 |
#define VIC1VECTPRIORITY25 (*((uint32_t volatile*)(0x38E01264)))
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269 |
#define VIC1VECTPRIORITY26 (*((uint32_t volatile*)(0x38E01268)))
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270 |
#define VIC1VECTPRIORITY27 (*((uint32_t volatile*)(0x38E0126C)))
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271 |
#define VIC1VECTPRIORITY28 (*((uint32_t volatile*)(0x38E01270)))
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272 |
#define VIC1VECTPRIORITY29 (*((uint32_t volatile*)(0x38E01274)))
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273 |
#define VIC1VECTPRIORITY30 (*((uint32_t volatile*)(0x38E01278)))
|
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274 |
#define VIC1VECTPRIORITY31 (*((uint32_t volatile*)(0x38E0127C)))
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275 |
#define VIC1ADDRESS (*((void* volatile*)(0x38E01F00)))
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276 |
|
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277 |
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|
278 |
/////GPIO/////
|
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|
279 |
#define PCON(i) (*((uint32_t volatile*)(0x3cf00000 + ((i) << 5))))
|
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|
280 |
#define PDAT(i) (*((uint32_t volatile*)(0x3cf00004 + ((i) << 5))))
|
|
|
281 |
#define PUNA(i) (*((uint32_t volatile*)(0x3cf00008 + ((i) << 5))))
|
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|
282 |
#define PUNB(i) (*((uint32_t volatile*)(0x3cf0000c + ((i) << 5))))
|
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|
283 |
#define PCON0 (*((uint32_t volatile*)(0x3cf00000)))
|
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|
284 |
#define PDAT0 (*((uint32_t volatile*)(0x3cf00004)))
|
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|
285 |
#define PCON1 (*((uint32_t volatile*)(0x3cf00020)))
|
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|
286 |
#define PDAT1 (*((uint32_t volatile*)(0x3cf00024)))
|
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|
287 |
#define PCON2 (*((uint32_t volatile*)(0x3cf00040)))
|
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|
288 |
#define PDAT2 (*((uint32_t volatile*)(0x3cf00044)))
|
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|
289 |
#define PCON3 (*((uint32_t volatile*)(0x3cf00060)))
|
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|
290 |
#define PDAT3 (*((uint32_t volatile*)(0x3cf00064)))
|
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|
291 |
#define PCON4 (*((uint32_t volatile*)(0x3cf00080)))
|
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|
292 |
#define PDAT4 (*((uint32_t volatile*)(0x3cf00084)))
|
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|
293 |
#define PCON5 (*((uint32_t volatile*)(0x3cf000a0)))
|
|
|
294 |
#define PDAT5 (*((uint32_t volatile*)(0x3cf000a4)))
|
|
|
295 |
#define PCON6 (*((uint32_t volatile*)(0x3cf000c0)))
|
|
|
296 |
#define PDAT6 (*((uint32_t volatile*)(0x3cf000c4)))
|
|
|
297 |
#define PCON7 (*((uint32_t volatile*)(0x3cf000e0)))
|
|
|
298 |
#define PDAT7 (*((uint32_t volatile*)(0x3cf000e4)))
|
|
|
299 |
#define PCON8 (*((uint32_t volatile*)(0x3cf00100)))
|
|
|
300 |
#define PDAT8 (*((uint32_t volatile*)(0x3cf00104)))
|
|
|
301 |
#define PCON9 (*((uint32_t volatile*)(0x3cf00120)))
|
|
|
302 |
#define PDAT9 (*((uint32_t volatile*)(0x3cf00124)))
|
|
|
303 |
#define PCONA (*((uint32_t volatile*)(0x3cf00140)))
|
|
|
304 |
#define PDATA (*((uint32_t volatile*)(0x3cf00144)))
|
|
|
305 |
#define PCONB (*((uint32_t volatile*)(0x3cf00160)))
|
|
|
306 |
#define PDATB (*((uint32_t volatile*)(0x3cf00164)))
|
|
|
307 |
#define PCONC (*((uint32_t volatile*)(0x3cf00180)))
|
|
|
308 |
#define PDATC (*((uint32_t volatile*)(0x3cf00184)))
|
|
|
309 |
#define PCOND (*((uint32_t volatile*)(0x3cf001a0)))
|
|
|
310 |
#define PDATD (*((uint32_t volatile*)(0x3cf001a4)))
|
|
|
311 |
#define PCONE (*((uint32_t volatile*)(0x3cf001c0)))
|
|
|
312 |
#define PDATE (*((uint32_t volatile*)(0x3cf001c4)))
|
|
|
313 |
#define PCONF (*((uint32_t volatile*)(0x3cf001e0)))
|
|
|
314 |
#define PDATF (*((uint32_t volatile*)(0x3cf001e4)))
|
|
|
315 |
#define GPIOCMD (*((uint32_t volatile*)(0x3cf00200)))
|
|
|
316 |
|
|
|
317 |
|
|
|
318 |
/////SPI/////
|
|
|
319 |
#define SPIBASE(i) ((i) == 2 ? 0x3d200000 : \
|
|
|
320 |
(i) == 1 ? 0x3ce00000 : \
|
|
|
321 |
0x3c300000)
|
|
|
322 |
#define SPICLKGATE(i) ((i) == 2 ? 0x2f : \
|
|
|
323 |
(i) == 1 ? 0x2b : \
|
|
|
324 |
0x22)
|
|
|
325 |
#define SPIDMA(i) ((i) == 2 ? 0xd : \
|
|
|
326 |
(i) == 1 ? 0xf : \
|
|
|
327 |
0x5)
|
|
|
328 |
#define SPICTRL(i) (*((uint32_t volatile*)(SPIBASE(i))))
|
|
|
329 |
#define SPISETUP(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x4)))
|
|
|
330 |
#define SPISTATUS(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x8)))
|
|
|
331 |
#define SPIUNKREG1(i) (*((uint32_t volatile*)(SPIBASE(i) + 0xc)))
|
|
|
332 |
#define SPITXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x10)))
|
|
|
333 |
#define SPIRXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x20)))
|
|
|
334 |
#define SPICLKDIV(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x30)))
|
|
|
335 |
#define SPIRXLIMIT(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x34)))
|
|
|
336 |
#define SPIUNKREG3(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x38)))
|
|
|
337 |
|
|
|
338 |
|
|
|
339 |
/////AES/////
|
|
|
340 |
#define AESCONTROL (*((uint32_t volatile*)(0x38c00000)))
|
|
|
341 |
#define AESGO (*((uint32_t volatile*)(0x38c00004)))
|
|
|
342 |
#define AESUNKREG0 (*((uint32_t volatile*)(0x38c00008)))
|
|
|
343 |
#define AESSTATUS (*((uint32_t volatile*)(0x38c0000c)))
|
|
|
344 |
#define AESUNKREG1 (*((uint32_t volatile*)(0x38c00010)))
|
|
|
345 |
#define AESKEYLEN (*((uint32_t volatile*)(0x38c00014)))
|
|
|
346 |
#define AESOUTSIZE (*((uint32_t volatile*)(0x38c00018)))
|
|
|
347 |
#define AESOUTADDR (*((void* volatile*)(0x38c00020)))
|
|
|
348 |
#define AESINSIZE (*((uint32_t volatile*)(0x38c00024)))
|
|
|
349 |
#define AESINADDR (*((const void* volatile*)(0x38c00028)))
|
|
|
350 |
#define AESAUXSIZE (*((uint32_t volatile*)(0x38c0002c)))
|
|
|
351 |
#define AESAUXADDR (*((void* volatile*)(0x38c00030)))
|
|
|
352 |
#define AESSIZE3 (*((uint32_t volatile*)(0x38c00034)))
|
|
|
353 |
#define AESKEY ((uint32_t volatile*)(0x38c0004c))
|
|
|
354 |
#define AESTYPE (*((uint32_t volatile*)(0x38c0006c)))
|
|
|
355 |
#define AESIV ((uint32_t volatile*)(0x38c00074))
|
|
|
356 |
#define AESTYPE2 (*((uint32_t volatile*)(0x38c00088)))
|
|
|
357 |
#define AESUNKREG2 (*((uint32_t volatile*)(0x38c0008c)))
|
|
|
358 |
|
|
|
359 |
|
|
|
360 |
/////SHA1/////
|
|
|
361 |
#define SHA1CONFIG (*((uint32_t volatile*)(0x38000000)))
|
|
|
362 |
#define SHA1RESET (*((uint32_t volatile*)(0x38000004)))
|
|
|
363 |
#define SHA1RESULT ((uint32_t volatile*)(0x38000020))
|
|
|
364 |
#define SHA1DATAIN ((uint32_t volatile*)(0x38000040))
|
|
|
365 |
|
|
|
366 |
|
|
|
367 |
/////DMA/////
|
|
|
368 |
struct dma_lli
|
|
|
369 |
{
|
|
|
370 |
void* srcaddr;
|
|
|
371 |
void* dstaddr;
|
|
|
372 |
const struct dma_lli* nextlli;
|
|
|
373 |
uint32_t control;
|
|
|
374 |
};
|
|
|
375 |
#define DMACINTSTS(d) (*((uint32_t volatile*)(0x38200000 + 0x1700000 * (d))))
|
|
|
376 |
#define DMACINTTCSTS(d) (*((uint32_t volatile*)(0x38200004 + 0x1700000 * (d))))
|
|
|
377 |
#define DMACINTTCCLR(d) (*((uint32_t volatile*)(0x38200008 + 0x1700000 * (d))))
|
|
|
378 |
#define DMACINTERRSTS(d) (*((uint32_t volatile*)(0x3820000c + 0x1700000 * (d))))
|
|
|
379 |
#define DMACINTERRCLR(d) (*((uint32_t volatile*)(0x38200010 + 0x1700000 * (d))))
|
|
|
380 |
#define DMACRAWINTTCSTS(d) (*((uint32_t volatile*)(0x38200014 + 0x1700000 * (d))))
|
|
|
381 |
#define DMACRAWINTERRSTS(d) (*((uint32_t volatile*)(0x38200018 + 0x1700000 * (d))))
|
|
|
382 |
#define DMACENABLEDCHANS(d) (*((uint32_t volatile*)(0x3820001c + 0x1700000 * (d))))
|
|
|
383 |
#define DMACSOFTBREQ(d) (*((uint32_t volatile*)(0x38200020 + 0x1700000 * (d))))
|
|
|
384 |
#define DMACSOFTSREQ(d) (*((uint32_t volatile*)(0x38200024 + 0x1700000 * (d))))
|
|
|
385 |
#define DMACSOFTLBREQ(d) (*((uint32_t volatile*)(0x38200028 + 0x1700000 * (d))))
|
|
|
386 |
#define DMACSOFTLSREQ(d) (*((uint32_t volatile*)(0x3820002c + 0x1700000 * (d))))
|
|
|
387 |
#define DMACCONFIG(d) (*((uint32_t volatile*)(0x38200030 + 0x1700000 * (d))))
|
|
|
388 |
#define DMACSYNC(d) (*((uint32_t volatile*)(0x38200034 + 0x1700000 * (d))))
|
|
|
389 |
#define DMACCLLI(d, c) (*((struct dma_lli volatile*)(0x38200100 + 0x1700000 * (d) + 0x20 * (c))))
|
|
|
390 |
#define DMACCSRCADDR(d, c) (*((const void* volatile*)(0x38200100 + 0x1700000 * (d) + 0x20 * (c))))
|
|
|
391 |
#define DMACCDESTADDR(d, c) (*((void* volatile*)(0x38200104 + 0x1700000 * (d) + 0x20 * (c))))
|
|
|
392 |
#define DMACCNEXTLLI(d, c) (*((const void* volatile*)(0x38200108 + 0x1700000 * (d) + 0x20 * (c))))
|
|
|
393 |
#define DMACCCONTROL(d, c) (*((uint32_t volatile*)(0x3820010c + 0x1700000 * (d) + 0x20 * (c))))
|
|
|
394 |
#define DMACCCONFIG(d, c) (*((uint32_t volatile*)(0x38200110 + 0x1700000 * (d) + 0x20 * (c))))
|
|
|
395 |
#define DMAC0INTSTS (*((uint32_t volatile*)(0x38200000)))
|
|
|
396 |
#define DMAC0INTTCSTS (*((uint32_t volatile*)(0x38200004)))
|
|
|
397 |
#define DMAC0INTTCCLR (*((uint32_t volatile*)(0x38200008)))
|
|
|
398 |
#define DMAC0INTERRSTS (*((uint32_t volatile*)(0x3820000c)))
|
|
|
399 |
#define DMAC0INTERRCLR (*((uint32_t volatile*)(0x38200010)))
|
|
|
400 |
#define DMAC0RAWINTTCSTS (*((uint32_t volatile*)(0x38200014)))
|
|
|
401 |
#define DMAC0RAWINTERRSTS (*((uint32_t volatile*)(0x38200018)))
|
|
|
402 |
#define DMAC0ENABLEDCHANS (*((uint32_t volatile*)(0x3820001c)))
|
|
|
403 |
#define DMAC0SOFTBREQ (*((uint32_t volatile*)(0x38200020)))
|
|
|
404 |
#define DMAC0SOFTSREQ (*((uint32_t volatile*)(0x38200024)))
|
|
|
405 |
#define DMAC0SOFTLBREQ (*((uint32_t volatile*)(0x38200028)))
|
|
|
406 |
#define DMAC0SOFTLSREQ (*((uint32_t volatile*)(0x3820002c)))
|
|
|
407 |
#define DMAC0CONFIG (*((uint32_t volatile*)(0x38200030)))
|
|
|
408 |
#define DMAC0SYNC (*((uint32_t volatile*)(0x38200034)))
|
|
|
409 |
#define DMAC0CLLI(c) (*((struct dma_lli volatile*)(0x38200100 + 0x20 * (c))))
|
|
|
410 |
#define DMAC0CSRCADDR(c) (*((const void* volatile*)(0x38200100 + 0x20 * (c))))
|
|
|
411 |
#define DMAC0CDESTADDR(c) (*((void* volatile*)(0x38200104 + 0x20 * (c))))
|
|
|
412 |
#define DMAC0CNEXTLLI(c) (*((const void* volatile*)(0x38200108 + 0x20 * (c))))
|
|
|
413 |
#define DMAC0CCONTROL(c) (*((uint32_t volatile*)(0x3820010c + 0x20 * (c))))
|
|
|
414 |
#define DMAC0CCONFIG(c) (*((uint32_t volatile*)(0x38200110 + 0x20 * (c))))
|
|
|
415 |
#define DMAC0C0LLI (*((struct dma_lli volatile*)(0x38200100)))
|
|
|
416 |
#define DMAC0C0SRCADDR (*((const void* volatile*)(0x38200100)))
|
|
|
417 |
#define DMAC0C0DESTADDR (*((void* volatile*)(0x38200104)))
|
|
|
418 |
#define DMAC0C0NEXTLLI (*((const struct dma_lli* volatile*)(0x38200108)))
|
|
|
419 |
#define DMAC0C0CONTROL (*((uint32_t volatile*)(0x3820010c)))
|
|
|
420 |
#define DMAC0C0CONFIG (*((uint32_t volatile*)(0x38200110)))
|
|
|
421 |
#define DMAC0C1LLI (*((struct dma_lli volatile*)(0x38200120)))
|
|
|
422 |
#define DMAC0C1SRCADDR (*((const void* volatile*)(0x38200120)))
|
|
|
423 |
#define DMAC0C1DESTADDR (*((void* volatile*)(0x38200124)))
|
|
|
424 |
#define DMAC0C1NEXTLLI (*((const struct dma_lli* volatile*)(0x38200128)))
|
|
|
425 |
#define DMAC0C1CONTROL (*((uint32_t volatile*)(0x3820012c)))
|
|
|
426 |
#define DMAC0C1CONFIG (*((uint32_t volatile*)(0x38200130)))
|
|
|
427 |
#define DMAC0C2LLI (*((struct dma_lli volatile*)(0x38200140)))
|
|
|
428 |
#define DMAC0C2SRCADDR (*((const void* volatile*)(0x38200140)))
|
|
|
429 |
#define DMAC0C2DESTADDR (*((void* volatile*)(0x38200144)))
|
|
|
430 |
#define DMAC0C2NEXTLLI (*((const struct dma_lli* volatile*)(0x38200148)))
|
|
|
431 |
#define DMAC0C2CONTROL (*((uint32_t volatile*)(0x3820014c)))
|
|
|
432 |
#define DMAC0C2CONFIG (*((uint32_t volatile*)(0x38200150)))
|
|
|
433 |
#define DMAC0C3LLI (*((struct dma_lli volatile*)(0x38200160)))
|
|
|
434 |
#define DMAC0C3SRCADDR (*((const void* volatile*)(0x38200160)))
|
|
|
435 |
#define DMAC0C3DESTADDR (*((void* volatile*)(0x38200164)))
|
|
|
436 |
#define DMAC0C3NEXTLLI (*((const struct dma_lli* volatile*)(0x38200168)))
|
|
|
437 |
#define DMAC0C3CONTROL (*((uint32_t volatile*)(0x3820016c)))
|
|
|
438 |
#define DMAC0C3CONFIG (*((uint32_t volatile*)(0x38200170)))
|
|
|
439 |
#define DMAC0C4LLI (*((struct dma_lli volatile*)(0x38200180)))
|
|
|
440 |
#define DMAC0C4SRCADDR (*((const void* volatile*)(0x38200180)))
|
|
|
441 |
#define DMAC0C4DESTADDR (*((void* volatile*)(0x38200184)))
|
|
|
442 |
#define DMAC0C4NEXTLLI (*((const struct dma_lli* volatile*)(0x38200188)))
|
|
|
443 |
#define DMAC0C4CONTROL (*((uint32_t volatile*)(0x3820018c)))
|
|
|
444 |
#define DMAC0C4CONFIG (*((uint32_t volatile*)(0x38200190)))
|
|
|
445 |
#define DMAC0C5LLI (*((struct dma_lli volatile*)(0x382001a0)))
|
|
|
446 |
#define DMAC0C5SRCADDR (*((const void* volatile*)(0x382001a0)))
|
|
|
447 |
#define DMAC0C5DESTADDR (*((void* volatile*)(0x382001a4)))
|
|
|
448 |
#define DMAC0C5NEXTLLI (*((const struct dma_lli* volatile*)(0x382001a8)))
|
|
|
449 |
#define DMAC0C5CONTROL (*((uint32_t volatile*)(0x382001ac)))
|
|
|
450 |
#define DMAC0C5CONFIG (*((uint32_t volatile*)(0x382001b0)))
|
|
|
451 |
#define DMAC0C6LLI (*((struct dma_lli volatile*)(0x382001c0)))
|
|
|
452 |
#define DMAC0C6SRCADDR (*((const void* volatile*)(0x382001c0)))
|
|
|
453 |
#define DMAC0C6DESTADDR (*((void* volatile*)(0x382001c4)))
|
|
|
454 |
#define DMAC0C6NEXTLLI (*((const struct dma_lli* volatile*)(0x382001c8)))
|
|
|
455 |
#define DMAC0C6CONTROL (*((uint32_t volatile*)(0x382001cc)))
|
|
|
456 |
#define DMAC0C6CONFIG (*((uint32_t volatile*)(0x382001d0)))
|
|
|
457 |
#define DMAC0C7LLI (*((struct dma_lli volatile*)(0x382001e0)))
|
|
|
458 |
#define DMAC0C7SRCADDR (*((const void* volatile*)(0x382001e0)))
|
|
|
459 |
#define DMAC0C7DESTADDR (*((void* volatile*)(0x382001e4)))
|
|
|
460 |
#define DMAC0C7NEXTLLI (*((const struct dma_lli* volatile*)(0x382001e8)))
|
|
|
461 |
#define DMAC0C7CONTROL (*((uint32_t volatile*)(0x382001ec)))
|
|
|
462 |
#define DMAC0C7CONFIG (*((uint32_t volatile*)(0x382001f0)))
|
|
|
463 |
#define DMAC1INTSTS (*((uint32_t volatile*)(0x39900000)))
|
|
|
464 |
#define DMAC1INTTCSTS (*((uint32_t volatile*)(0x39900004)))
|
|
|
465 |
#define DMAC1INTTCCLR (*((uint32_t volatile*)(0x39900008)))
|
|
|
466 |
#define DMAC1INTERRSTS (*((uint32_t volatile*)(0x3990000c)))
|
|
|
467 |
#define DMAC1INTERRCLR (*((uint32_t volatile*)(0x39900010)))
|
|
|
468 |
#define DMAC1RAWINTTCSTS (*((uint32_t volatile*)(0x39900014)))
|
|
|
469 |
#define DMAC1RAWINTERRSTS (*((uint32_t volatile*)(0x39900018)))
|
|
|
470 |
#define DMAC1ENABLEDCHANS (*((uint32_t volatile*)(0x3990001c)))
|
|
|
471 |
#define DMAC1SOFTBREQ (*((uint32_t volatile*)(0x39900020)))
|
|
|
472 |
#define DMAC1SOFTSREQ (*((uint32_t volatile*)(0x39900024)))
|
|
|
473 |
#define DMAC1SOFTLBREQ (*((uint32_t volatile*)(0x39900028)))
|
|
|
474 |
#define DMAC1SOFTLSREQ (*((uint32_t volatile*)(0x3990002c)))
|
|
|
475 |
#define DMAC1CONFIG (*((uint32_t volatile*)(0x39900030)))
|
|
|
476 |
#define DMAC1SYNC (*((uint32_t volatile*)(0x39900034)))
|
|
|
477 |
#define DMAC1CLLI(c) (*((struct dma_lli volatile*)(0x39900100 + 0x20 * (c))))
|
|
|
478 |
#define DMAC1CSRCADDR(c) (*((const void* volatile*)(0x39900100 + 0x20 * (c))))
|
|
|
479 |
#define DMAC1CDESTADDR(c) (*((void* volatile*)(0x39900104 + 0x20 * (c))))
|
|
|
480 |
#define DMAC1CNEXTLLI(c) (*((const void* volatile*)(0x39900108 + 0x20 * (c))))
|
|
|
481 |
#define DMAC1CCONTROL(c) (*((uint32_t volatile*)(0x3990010c + 0x20 * (c))))
|
|
|
482 |
#define DMAC1CCONFIG(c) (*((uint32_t volatile*)(0x39900110 + 0x20 * (c))))
|
|
|
483 |
#define DMAC1C0LLI (*((struct dma_lli volatile*)(0x39900100)))
|
|
|
484 |
#define DMAC1C0SRCADDR (*((const void* volatile*)(0x39900100)))
|
|
|
485 |
#define DMAC1C0DESTADDR (*((void* volatile*)(0x39900104)))
|
|
|
486 |
#define DMAC1C0NEXTLLI (*((const struct dma_lli* volatile*)(0x39900108)))
|
|
|
487 |
#define DMAC1C0CONTROL (*((uint32_t volatile*)(0x3990010c)))
|
|
|
488 |
#define DMAC1C0CONFIG (*((uint32_t volatile*)(0x39900110)))
|
|
|
489 |
#define DMAC1C1LLI (*((struct dma_lli volatile*)(0x39900120)))
|
|
|
490 |
#define DMAC1C1SRCADDR (*((const void* volatile*)(0x39900120)))
|
|
|
491 |
#define DMAC1C1DESTADDR (*((void* volatile*)(0x39900124)))
|
|
|
492 |
#define DMAC1C1NEXTLLI (*((const struct dma_lli* volatile*)(0x39900128)))
|
|
|
493 |
#define DMAC1C1CONTROL (*((uint32_t volatile*)(0x3990012c)))
|
|
|
494 |
#define DMAC1C1CONFIG (*((uint32_t volatile*)(0x39900130)))
|
|
|
495 |
#define DMAC1C2LLI (*((struct dma_lli volatile*)(0x39900140)))
|
|
|
496 |
#define DMAC1C2SRCADDR (*((const void* volatile*)(0x39900140)))
|
|
|
497 |
#define DMAC1C2DESTADDR (*((void* volatile*)(0x39900144)))
|
|
|
498 |
#define DMAC1C2NEXTLLI (*((const struct dma_lli* volatile*)(0x39900148)))
|
|
|
499 |
#define DMAC1C2CONTROL (*((uint32_t volatile*)(0x3990014c)))
|
|
|
500 |
#define DMAC1C2CONFIG (*((uint32_t volatile*)(0x39900150)))
|
|
|
501 |
#define DMAC1C3LLI (*((struct dma_lli volatile*)(0x39900160)))
|
|
|
502 |
#define DMAC1C3SRCADDR (*((const void* volatile*)(0x39900160)))
|
|
|
503 |
#define DMAC1C3DESTADDR (*((void* volatile*)(0x39900164)))
|
|
|
504 |
#define DMAC1C3NEXTLLI (*((volatile void**)(0x39900168)))
|
|
|
505 |
#define DMAC1C3CONTROL (*((uint32_t volatile*)(0x3990016c)))
|
|
|
506 |
#define DMAC1C3CONFIG (*((uint32_t volatile*)(0x39900170)))
|
|
|
507 |
#define DMAC1C4LLI (*((struct dma_lli volatile*)(0x39900180)))
|
|
|
508 |
#define DMAC1C4SRCADDR (*((const void* volatile*)(0x39900180)))
|
|
|
509 |
#define DMAC1C4DESTADDR (*((void* volatile*)(0x39900184)))
|
|
|
510 |
#define DMAC1C4NEXTLLI (*((const struct dma_lli* volatile*)(0x39900188)))
|
|
|
511 |
#define DMAC1C4CONTROL (*((uint32_t volatile*)(0x3990018c)))
|
|
|
512 |
#define DMAC1C4CONFIG (*((uint32_t volatile*)(0x39900190)))
|
|
|
513 |
#define DMAC1C5LLI (*((struct dma_lli volatile*)(0x399001a0)))
|
|
|
514 |
#define DMAC1C5SRCADDR (*((const void* volatile*)(0x399001a0)))
|
|
|
515 |
#define DMAC1C5DESTADDR (*((void* volatile*)(0x399001a4)))
|
|
|
516 |
#define DMAC1C5NEXTLLI (*((const struct dma_lli* volatile*)(0x399001a8)))
|
|
|
517 |
#define DMAC1C5CONTROL (*((uint32_t volatile*)(0x399001ac)))
|
|
|
518 |
#define DMAC1C5CONFIG (*((uint32_t volatile*)(0x399001b0)))
|
|
|
519 |
#define DMAC1C6LLI (*((struct dma_lli volatile*)(0x399001c0)))
|
|
|
520 |
#define DMAC1C6SRCADDR (*((const void* volatile*)(0x399001c0)))
|
|
|
521 |
#define DMAC1C6DESTADDR (*((void* volatile*)(0x399001c4)))
|
|
|
522 |
#define DMAC1C6NEXTLLI (*((const struct dma_lli* volatile*)(0x399001c8)))
|
|
|
523 |
#define DMAC1C6CONTROL (*((uint32_t volatile*)(0x399001cc)))
|
|
|
524 |
#define DMAC1C6CONFIG (*((uint32_t volatile*)(0x399001d0)))
|
|
|
525 |
#define DMAC1C7LLI (*((struct dma_lli volatile*)(0x399001e0)))
|
|
|
526 |
#define DMAC1C7SRCADDR (*((const void* volatile*)(0x399001e0)))
|
|
|
527 |
#define DMAC1C7DESTADDR (*((void* volatile*)(0x399001e4)))
|
|
|
528 |
#define DMAC1C7NEXTLLI (*((const struct dma_lli* volatile*)(0x399001e8)))
|
|
|
529 |
#define DMAC1C7CONTROL (*((uint32_t volatile*)(0x399001ec)))
|
|
|
530 |
#define DMAC1C7CONFIG (*((uint32_t volatile*)(0x399001f0)))
|
|
|
531 |
|
|
|
532 |
|
|
|
533 |
/////LCD/////
|
|
|
534 |
#define LCDCON (*((uint32_t volatile*)(0x38300000)))
|
|
|
535 |
#define LCDWCMD (*((uint32_t volatile*)(0x38300004)))
|
|
|
536 |
#define LCDSTATUS (*((uint32_t volatile*)(0x3830001c)))
|
|
|
537 |
#define LCDPHTIME (*((uint32_t volatile*)(0x38300010)))
|
|
|
538 |
#define LCDWDATA (*((uint32_t volatile*)(0x38300040)))
|
|
|
539 |
|
|
|
540 |
/////ATA/////
|
|
|
541 |
#define ATA_CONTROL (*((uint32_t volatile*)(0x38700000)))
|
|
|
542 |
#define ATA_STATUS (*((uint32_t volatile*)(0x38700004)))
|
|
|
543 |
#define ATA_COMMAND (*((uint32_t volatile*)(0x38700008)))
|
|
|
544 |
#define ATA_SWRST (*((uint32_t volatile*)(0x3870000c)))
|
|
|
545 |
#define ATA_IRQ (*((uint32_t volatile*)(0x38700010)))
|
|
|
546 |
#define ATA_IRQ_MASK (*((uint32_t volatile*)(0x38700014)))
|
|
|
547 |
#define ATA_CFG (*((uint32_t volatile*)(0x38700018)))
|
|
|
548 |
#define ATA_MDMA_TIME (*((uint32_t volatile*)(0x38700028)))
|
|
|
549 |
#define ATA_PIO_TIME (*((uint32_t volatile*)(0x3870002c)))
|
|
|
550 |
#define ATA_UDMA_TIME (*((uint32_t volatile*)(0x38700030)))
|
|
|
551 |
#define ATA_XFR_NUM (*((uint32_t volatile*)(0x38700034)))
|
|
|
552 |
#define ATA_XFR_CNT (*((uint32_t volatile*)(0x38700038)))
|
|
|
553 |
#define ATA_TBUF_START (*((void* volatile*)(0x3870003c)))
|
|
|
554 |
#define ATA_TBUF_SIZE (*((uint32_t volatile*)(0x38700040)))
|
|
|
555 |
#define ATA_SBUF_START (*((void* volatile*)(0x38700044)))
|
|
|
556 |
#define ATA_SBUF_SIZE (*((uint32_t volatile*)(0x38700048)))
|
|
|
557 |
#define ATA_CADR_TBUF (*((void* volatile*)(0x3870004c)))
|
|
|
558 |
#define ATA_CADR_SBUF (*((void* volatile*)(0x38700050)))
|
|
|
559 |
#define ATA_PIO_DTR (*((uint32_t volatile*)(0x38700054)))
|
|
|
560 |
#define ATA_PIO_FED (*((uint32_t volatile*)(0x38700058)))
|
|
|
561 |
#define ATA_PIO_SCR (*((uint32_t volatile*)(0x3870005c)))
|
|
|
562 |
#define ATA_PIO_LLR (*((uint32_t volatile*)(0x38700060)))
|
|
|
563 |
#define ATA_PIO_LMR (*((uint32_t volatile*)(0x38700064)))
|
|
|
564 |
#define ATA_PIO_LHR (*((uint32_t volatile*)(0x38700068)))
|
|
|
565 |
#define ATA_PIO_DVR (*((uint32_t volatile*)(0x3870006c)))
|
|
|
566 |
#define ATA_PIO_CSD (*((uint32_t volatile*)(0x38700070)))
|
|
|
567 |
#define ATA_PIO_DAD (*((uint32_t volatile*)(0x38700074)))
|
|
|
568 |
#define ATA_PIO_READY (*((uint32_t volatile*)(0x38700078)))
|
|
|
569 |
#define ATA_PIO_RDATA (*((uint32_t volatile*)(0x3870007c)))
|
|
|
570 |
#define ATA_BUS_FIFO_STATUS (*((uint32_t volatile*)(0x38700080)))
|
|
|
571 |
#define ATA_FIFO_STATUS (*((uint32_t volatile*)(0x38700084)))
|
|
|
572 |
#define ATA_DMA_ADDR (*((void* volatile*)(0x38700088)))
|
|
|
573 |
|
|
|
574 |
|
| 629 |
theseven |
575 |
/////SDCI/////
|
| 642 |
theseven |
576 |
#define SDCI_CTRL (*((uint32_t volatile*)(0x38b00000)))
|
|
|
577 |
#define SDCI_DCTRL (*((uint32_t volatile*)(0x38b00004)))
|
|
|
578 |
#define SDCI_CMD (*((uint32_t volatile*)(0x38b00008)))
|
|
|
579 |
#define SDCI_ARGU (*((uint32_t volatile*)(0x38b0000c)))
|
|
|
580 |
#define SDCI_STATE (*((uint32_t volatile*)(0x38b00010)))
|
|
|
581 |
#define SDCI_STAC (*((uint32_t volatile*)(0x38b00014)))
|
|
|
582 |
#define SDCI_DSTA (*((uint32_t volatile*)(0x38b00018)))
|
|
|
583 |
#define SDCI_FSTA (*((uint32_t volatile*)(0x38b0001c)))
|
|
|
584 |
#define SDCI_RESP0 (*((uint32_t volatile*)(0x38b00020)))
|
|
|
585 |
#define SDCI_RESP1 (*((uint32_t volatile*)(0x38b00024)))
|
|
|
586 |
#define SDCI_RESP2 (*((uint32_t volatile*)(0x38b00028)))
|
|
|
587 |
#define SDCI_RESP3 (*((uint32_t volatile*)(0x38b0002c)))
|
|
|
588 |
#define SDCI_CDIV (*((uint32_t volatile*)(0x38b00030)))
|
|
|
589 |
#define SDCI_SDIO_CSR (*((uint32_t volatile*)(0x38b00034)))
|
|
|
590 |
#define SDCI_IRQ (*((uint32_t volatile*)(0x38b00038)))
|
|
|
591 |
#define SDCI_IRQ_MASK (*((uint32_t volatile*)(0x38b0003c)))
|
|
|
592 |
#define SDCI_DATA (*((uint32_t volatile*)(0x38b00040)))
|
|
|
593 |
#define SDCI_DMAADDR (*((void* volatile*)(0x38b00044)))
|
|
|
594 |
#define SDCI_DMASIZE (*((uint32_t volatile*)(0x38b00048)))
|
|
|
595 |
#define SDCI_DMACOUNT (*((uint32_t volatile*)(0x38b0004c)))
|
|
|
596 |
#define SDCI_RESET (*((uint32_t volatile*)(0x38b0006c)))
|
| 629 |
theseven |
597 |
|
| 642 |
theseven |
598 |
#define SDCI_CTRL_SDCIEN BIT(0)
|
|
|
599 |
#define SDCI_CTRL_CARD_TYPE_MASK BIT(1)
|
|
|
600 |
#define SDCI_CTRL_CARD_TYPE_SD 0
|
|
|
601 |
#define SDCI_CTRL_CARD_TYPE_MMC BIT(1)
|
|
|
602 |
#define SDCI_CTRL_BUS_WIDTH_MASK BITRANGE(2, 3)
|
|
|
603 |
#define SDCI_CTRL_BUS_WIDTH_1BIT 0
|
|
|
604 |
#define SDCI_CTRL_BUS_WIDTH_4BIT BIT(2)
|
|
|
605 |
#define SDCI_CTRL_BUS_WIDTH_8BIT BIT(3)
|
|
|
606 |
#define SDCI_CTRL_DMA_EN BIT(4)
|
|
|
607 |
#define SDCI_CTRL_L_ENDIAN BIT(5)
|
|
|
608 |
#define SDCI_CTRL_DMA_REQ_CON_MASK BIT(6)
|
|
|
609 |
#define SDCI_CTRL_DMA_REQ_CON_NEMPTY 0
|
|
|
610 |
#define SDCI_CTRL_DMA_REQ_CON_FULL BIT(6)
|
|
|
611 |
#define SDCI_CTRL_CLK_SEL_MASK BIT(7)
|
|
|
612 |
#define SDCI_CTRL_CLK_SEL_PCLK 0
|
|
|
613 |
#define SDCI_CTRL_CLK_SEL_SDCLK BIT(7)
|
|
|
614 |
#define SDCI_CTRL_BIT_8 BIT(8)
|
|
|
615 |
#define SDCI_CTRL_BIT_14 BIT(14)
|
| 629 |
theseven |
616 |
|
| 642 |
theseven |
617 |
#define SDCI_DCTRL_TXFIFORST BIT(0)
|
|
|
618 |
#define SDCI_DCTRL_RXFIFORST BIT(1)
|
|
|
619 |
#define SDCI_DCTRL_TRCONT_MASK BITRANGE(4, 5)
|
|
|
620 |
#define SDCI_DCTRL_TRCONT_TX BIT(4)
|
|
|
621 |
#define SDCI_DCTRL_BUS_TEST_MASK BITRANGE(6, 7)
|
|
|
622 |
#define SDCI_DCTRL_BUS_TEST_TX BIT(6)
|
|
|
623 |
#define SDCI_DCTRL_BUS_TEST_RX BIT(7)
|
|
|
624 |
|
|
|
625 |
#define SDCI_CDIV_CLKDIV_MASK BITRANGE(0, 7)
|
|
|
626 |
#define SDCI_CDIV_CLKDIV(x) ((x) >> 1)
|
|
|
627 |
#define SDCI_CDIV_CLKDIV_2 BIT(0)
|
|
|
628 |
#define SDCI_CDIV_CLKDIV_4 BIT(1)
|
|
|
629 |
#define SDCI_CDIV_CLKDIV_8 BIT(2)
|
|
|
630 |
#define SDCI_CDIV_CLKDIV_16 BIT(3)
|
|
|
631 |
#define SDCI_CDIV_CLKDIV_32 BIT(4)
|
|
|
632 |
#define SDCI_CDIV_CLKDIV_64 BIT(5)
|
|
|
633 |
#define SDCI_CDIV_CLKDIV_128 BIT(6)
|
|
|
634 |
#define SDCI_CDIV_CLKDIV_256 BIT(7)
|
|
|
635 |
|
|
|
636 |
#define SDCI_CMD_CMD_NUM_MASK BITRANGE(0, 5)
|
|
|
637 |
#define SDCI_CMD_CMD_NUM_SHIFT 0
|
|
|
638 |
#define SDCI_CMD_CMD_NUM(x) (x)
|
|
|
639 |
#define SDCI_CMD_CMD_TYPE_MASK BITRANGE(6, 7)
|
|
|
640 |
#define SDCI_CMD_CMD_TYPE_BC 0
|
|
|
641 |
#define SDCI_CMD_CMD_TYPE_BCR BIT(6)
|
|
|
642 |
#define SDCI_CMD_CMD_TYPE_AC BIT(7)
|
|
|
643 |
#define SDCI_CMD_CMD_TYPE_ADTC (BIT(6) | BIT(7))
|
|
|
644 |
#define SDCI_CMD_CMD_RD_WR BIT(8)
|
|
|
645 |
#define SDCI_CMD_RES_TYPE_MASK BITRANGE(16, 18)
|
|
|
646 |
#define SDCI_CMD_RES_TYPE_NONE 0
|
|
|
647 |
#define SDCI_CMD_RES_TYPE_R1 BIT(16)
|
|
|
648 |
#define SDCI_CMD_RES_TYPE_R2 BIT(17)
|
|
|
649 |
#define SDCI_CMD_RES_TYPE_R3 (BIT(16) | BIT(17))
|
|
|
650 |
#define SDCI_CMD_RES_TYPE_R4 BIT(18)
|
|
|
651 |
#define SDCI_CMD_RES_TYPE_R5 (BIT(16) | BIT(18))
|
|
|
652 |
#define SDCI_CMD_RES_TYPE_R6 (BIT(17) | BIT(18))
|
|
|
653 |
#define SDCI_CMD_RES_BUSY BIT(19)
|
|
|
654 |
#define SDCI_CMD_RES_SIZE_MASK BIT(20)
|
|
|
655 |
#define SDCI_CMD_RES_SIZE_48 0
|
|
|
656 |
#define SDCI_CMD_RES_SIZE_136 BIT(20)
|
|
|
657 |
#define SDCI_CMD_NCR_NID_MASK BIT(21)
|
|
|
658 |
#define SDCI_CMD_NCR_NID_NCR 0
|
|
|
659 |
#define SDCI_CMD_NCR_NID_NID BIT(21)
|
|
|
660 |
#define SDCI_CMD_CMDSTR BIT(31)
|
|
|
661 |
|
|
|
662 |
#define SDCI_STATE_DAT_STATE_MASK BITRANGE(0, 3)
|
|
|
663 |
#define SDCI_STATE_DAT_STATE_IDLE 0
|
|
|
664 |
#define SDCI_STATE_DAT_STATE_DAT_RCV BIT(0)
|
|
|
665 |
#define SDCI_STATE_DAT_STATE_CRC_RCV BIT(1)
|
|
|
666 |
#define SDCI_STATE_DAT_STATE_DAT_END (BIT(0) | BIT(1))
|
|
|
667 |
#define SDCI_STATE_DAT_STATE_DAT_SET BIT(2)
|
|
|
668 |
#define SDCI_STATE_DAT_STATE_DAT_OUT (BIT(0) | BIT(2))
|
|
|
669 |
#define SDCI_STATE_DAT_STATE_CRC_TIME (BIT(1) | BIT(2))
|
|
|
670 |
#define SDCI_STATE_DAT_STATE_CRC_OUT (BIT(0) | BIT(1) | BIT(2))
|
|
|
671 |
#define SDCI_STATE_DAT_STATE_ENDB_OUT BIT(3)
|
|
|
672 |
#define SDCI_STATE_DAT_STATE_ENDB_STOD (BIT(0) | BIT(3))
|
|
|
673 |
#define SDCI_STATE_DAT_STATE_DAT_CRCR (BIT(1) | BIT(3))
|
|
|
674 |
#define SDCI_STATE_DAT_STATE_CARD_PRG (BIT(0) | BIT(1) | BIT(3))
|
|
|
675 |
#define SDCI_STATE_DAT_STATE_DAT_BUSY (BIT(2) | BIT(3))
|
|
|
676 |
#define SDCI_STATE_CMD_STATE_MASK (BIT(4) | BIT(5) | BIT(6))
|
|
|
677 |
#define SDCI_STATE_CMD_STATE_CMD_IDLE 0
|
|
|
678 |
#define SDCI_STATE_CMD_STATE_CMD_CMDO BIT(4)
|
|
|
679 |
#define SDCI_STATE_CMD_STATE_CMD_CRCO BIT(5)
|
|
|
680 |
#define SDCI_STATE_CMD_STATE_CMD_TOUT (BIT(4) | BIT(5))
|
|
|
681 |
#define SDCI_STATE_CMD_STATE_CMD_RESR BIT(6)
|
|
|
682 |
#define SDCI_STATE_CMD_STATE_CMD_INTV (BIT(4) | BIT(6))
|
|
|
683 |
|
|
|
684 |
#define SDCI_STAC_CLR_CMDEND BIT(2)
|
|
|
685 |
#define SDCI_STAC_CLR_BIT_3 BIT(3)
|
|
|
686 |
#define SDCI_STAC_CLR_RESEND BIT(4)
|
|
|
687 |
#define SDCI_STAC_CLR_DATEND BIT(6)
|
|
|
688 |
#define SDCI_STAC_CLR_DAT_CRCEND BIT(7)
|
|
|
689 |
#define SDCI_STAC_CLR_CRC_STAEND BIT(8)
|
|
|
690 |
#define SDCI_STAC_CLR_RESTOUTE BIT(15)
|
|
|
691 |
#define SDCI_STAC_CLR_RESENDE BIT(16)
|
|
|
692 |
#define SDCI_STAC_CLR_RESINDE BIT(17)
|
|
|
693 |
#define SDCI_STAC_CLR_RESCRCE BIT(18)
|
|
|
694 |
#define SDCI_STAC_CLR_WR_DATCRCE BIT(22)
|
|
|
695 |
#define SDCI_STAC_CLR_RD_DATCRCE BIT(23)
|
|
|
696 |
#define SDCI_STAC_CLR_RD_DATENDE0 BIT(24)
|
|
|
697 |
#define SDCI_STAC_CLR_RD_DATENDE1 BIT(25)
|
|
|
698 |
#define SDCI_STAC_CLR_RD_DATENDE2 BIT(26)
|
|
|
699 |
#define SDCI_STAC_CLR_RD_DATENDE3 BIT(27)
|
|
|
700 |
#define SDCI_STAC_CLR_RD_DATENDE4 BIT(28)
|
|
|
701 |
#define SDCI_STAC_CLR_RD_DATENDE5 BIT(29)
|
|
|
702 |
#define SDCI_STAC_CLR_RD_DATENDE6 BIT(30)
|
|
|
703 |
#define SDCI_STAC_CLR_RD_DATENDE7 BIT(31)
|
|
|
704 |
|
|
|
705 |
#define SDCI_DSTA_CMDRDY BIT(0)
|
|
|
706 |
#define SDCI_DSTA_CMDPRO BIT(1)
|
|
|
707 |
#define SDCI_DSTA_CMDEND BIT(2)
|
|
|
708 |
#define SDCI_DSTA_RESPRO BIT(3)
|
|
|
709 |
#define SDCI_DSTA_RESEND BIT(4)
|
|
|
710 |
#define SDCI_DSTA_DATPRO BIT(5)
|
|
|
711 |
#define SDCI_DSTA_DATEND BIT(6)
|
|
|
712 |
#define SDCI_DSTA_DAT_CRCEND BIT(7)
|
|
|
713 |
#define SDCI_DSTA_CRC_STAEND BIT(8)
|
|
|
714 |
#define SDCI_DSTA_DAT_BUSY BIT(9)
|
|
|
715 |
#define SDCI_DSTA_SDCLK_HOLD BIT(12)
|
|
|
716 |
#define SDCI_DSTA_DAT0_STATUS BIT(13)
|
|
|
717 |
#define SDCI_DSTA_WP_DECT_INPUT BIT(14)
|
|
|
718 |
#define SDCI_DSTA_RESTOUTE BIT(15)
|
|
|
719 |
#define SDCI_DSTA_RESENDE BIT(16)
|
|
|
720 |
#define SDCI_DSTA_RESINDE BIT(17)
|
|
|
721 |
#define SDCI_DSTA_RESCRCE BIT(18)
|
|
|
722 |
#define SDCI_DSTA_WR_CRC_STATUS_MASK BITRANGE(19, 21)
|
|
|
723 |
#define SDCI_DSTA_WR_CRC_STATUS_OK BIT(20)
|
|
|
724 |
#define SDCI_DSTA_WR_CRC_STATUS_TXERR (BIT(19) | BIT(21))
|
|
|
725 |
#define SDCI_DSTA_WR_CRC_STATUS_CARDERR (BIT(19) | BIT(20) | BIT(21))
|
|
|
726 |
#define SDCI_DSTA_WR_DATCRCE BIT(22)
|
|
|
727 |
#define SDCI_DSTA_RD_DATCRCE BIT(23)
|
|
|
728 |
#define SDCI_DSTA_RD_DATENDE0 BIT(24)
|
|
|
729 |
#define SDCI_DSTA_RD_DATENDE1 BIT(25)
|
|
|
730 |
#define SDCI_DSTA_RD_DATENDE2 BIT(26)
|
|
|
731 |
#define SDCI_DSTA_RD_DATENDE3 BIT(27)
|
|
|
732 |
#define SDCI_DSTA_RD_DATENDE4 BIT(28)
|
|
|
733 |
#define SDCI_DSTA_RD_DATENDE5 BIT(29)
|
|
|
734 |
#define SDCI_DSTA_RD_DATENDE6 BIT(30)
|
|
|
735 |
#define SDCI_DSTA_RD_DATENDE7 BIT(31)
|
|
|
736 |
|
|
|
737 |
#define SDCI_FSTA_RX_FIFO_EMPTY BIT(0)
|
|
|
738 |
#define SDCI_FSTA_RX_FIFO_FULL BIT(1)
|
|
|
739 |
#define SDCI_FSTA_TX_FIFO_EMPTY BIT(2)
|
|
|
740 |
#define SDCI_FSTA_TX_FIFO_FULL BIT(3)
|
|
|
741 |
|
|
|
742 |
#define SDCI_SDIO_CSR_SDIO_RW_EN BIT(0)
|
|
|
743 |
#define SDCI_SDIO_CSR_SDIO_INT_EN BIT(1)
|
|
|
744 |
#define SDCI_SDIO_CSR_SDIO_RW_REQ BIT(2)
|
|
|
745 |
#define SDCI_SDIO_CSR_SDIO_RW_STOP BIT(3)
|
|
|
746 |
#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MASK BIT(4)
|
|
|
747 |
#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MORE 0
|
|
|
748 |
#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_XACT BIT(4)
|
|
|
749 |
|
|
|
750 |
#define SDCI_IRQ_DAT_DONE_INT BIT(0)
|
|
|
751 |
#define SDCI_IRQ_IOCARD_IRQ_INT BIT(1)
|
|
|
752 |
#define SDCI_IRQ_READ_WAIT_INT BIT(2)
|
|
|
753 |
|
|
|
754 |
#define SDCI_IRQ_MASK_MASK_DAT_DONE_INT BIT(0)
|
|
|
755 |
#define SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT BIT(1)
|
|
|
756 |
#define SDCI_IRQ_MASK_MASK_READ_WAIT_INT BIT(2)
|
|
|
757 |
|
|
|
758 |
|
| 511 |
theseven |
759 |
/////CLICKWHEEL/////
|
|
|
760 |
#define WHEEL00 (*((uint32_t volatile*)(0x3C200000)))
|
|
|
761 |
#define WHEEL04 (*((uint32_t volatile*)(0x3C200004)))
|
|
|
762 |
#define WHEEL08 (*((uint32_t volatile*)(0x3C200008)))
|
|
|
763 |
#define WHEEL0C (*((uint32_t volatile*)(0x3C20000C)))
|
|
|
764 |
#define WHEEL10 (*((uint32_t volatile*)(0x3C200010)))
|
|
|
765 |
#define WHEELINT (*((uint32_t volatile*)(0x3C200014)))
|
|
|
766 |
#define WHEELRX (*((uint32_t volatile*)(0x3C200018)))
|
|
|
767 |
#define WHEELTX (*((uint32_t volatile*)(0x3C20001C)))
|
|
|
768 |
|
|
|
769 |
|
| 684 |
theseven |
770 |
/////UART/////
|
| 746 |
theseven |
771 |
#define ULCON (*((uint32_t volatile*)0x3cc00000))
|
|
|
772 |
#define UCON (*((uint32_t volatile*)0x3cc00004))
|
|
|
773 |
#define UFCON (*((uint32_t volatile*)0x3cc00008))
|
|
|
774 |
#define UMCON (*((uint32_t volatile*)0x3cc0000c))
|
|
|
775 |
#define UFSTAT (*((uint32_t volatile*)0x3cc00018))
|
|
|
776 |
#define UTXH (*((uint8_t volatile*)0x3cc00020))
|
|
|
777 |
#define URXH (*((uint8_t volatile*)0x3cc00024))
|
|
|
778 |
#define UBRDIV (*((uint32_t volatile*)0x3cc00028))
|
| 684 |
theseven |
779 |
|
|
|
780 |
|
| 511 |
theseven |
781 |
/////CLOCK GATES/////
|
| 560 |
theseven |
782 |
#define CLOCKGATE_LCD 1
|
| 511 |
theseven |
783 |
#define CLOCKGATE_USB_1 2
|
| 560 |
theseven |
784 |
#define CLOCKGATE_DMA(x) 25
|
|
|
785 |
#define CLOCKGATE_DMA_0 25
|
| 511 |
theseven |
786 |
#define CLOCKGATE_USB_2 35
|
| 560 |
theseven |
787 |
#define CLOCKGATE_I2C(x) 36
|
|
|
788 |
#define CLOCKGATE_I2C_0 36
|
|
|
789 |
#define CLOCKGATE_SPI(x) ((i) == 2 ? 47 : (i) == 1 ? 43 : 34)
|
|
|
790 |
#define CLOCKGATE_SPI_0 34
|
|
|
791 |
#define CLOCKGATE_SPI_1 43
|
|
|
792 |
#define CLOCKGATE_SPI_2 47
|
| 511 |
theseven |
793 |
|
|
|
794 |
|
|
|
795 |
/////INTERRUPTS/////
|
|
|
796 |
#define IRQ_TIMER 8
|
|
|
797 |
#define IRQ_USB_FUNC 19
|
|
|
798 |
#define IRQ_DMAC(d) 16 + d
|
|
|
799 |
#define IRQ_DMAC0 16
|
|
|
800 |
#define IRQ_DMAC1 17
|
|
|
801 |
#define IRQ_WHEEL 23
|
|
|
802 |
#define IRQ_ATA 29
|
| 629 |
theseven |
803 |
#define IRQ_MMC 44
|
| 511 |
theseven |
804 |
|
|
|
805 |
|
|
|
806 |
#endif
|