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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 Dave Chapman
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "global.h"
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#include "thread.h"
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#include "disk.h"
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#include "storage.h"
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#include "storage_ata-target.h"
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#include "timer.h"
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#include "malloc.h"
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#include "constants/mmc.h"
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#include "../ipodnano3g/s5l8702.h"
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#ifndef ATA_RETRIES
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#define ATA_RETRIES 3
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#endif
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#define CEATA_POWERUP_TIMEOUT 30000000
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#define CEATA_COMMAND_TIMEOUT 1000000
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#define CEATA_DAT_NONBUSY_TIMEOUT 5000000
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#define CEATA_MMC_RCA 1
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/** static, private data **/
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static uint8_t ceata_taskfile[16] CACHEALIGN_ATTR;
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uint16_t ata_identify_data[0x100] CACHEALIGN_ATTR;
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bool ceata;
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bool ata_lba48;
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bool ata_dma;
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uint64_t ata_total_sectors;
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struct mutex ata_mutex;
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static struct wakeup ata_wakeup;
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static uint32_t ata_dma_flags;
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static long ata_last_activity_value = -1;
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static long ata_sleep_timeout = 20000000;
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static struct scheduler_thread ata_thread_handle;
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static uint32_t ata_stack[0x80] STACK_ATTR;
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static bool ata_powered;
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static int ata_retries = ATA_RETRIES;
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static bool ata_error_srst = true;
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static struct wakeup mmc_wakeup;
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static struct wakeup mmc_comp_wakeup;
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#ifdef ATA_HAVE_BBT
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#include "panic.h"
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uint16_t (*ata_bbt)[0x20];
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uint64_t ata_virtual_sectors;
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uint32_t ata_last_offset;
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uint64_t ata_last_phys;
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static uint16_t ata_read_cbr(uint32_t volatile* reg);
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int ata_bbt_read_sectors(uint32_t sector, uint32_t count, void* buffer)
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{
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if (ata_last_phys != sector - 1 && ata_last_phys > sector - 64) ata_reset();
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int rc = ata_rw_sectors_internal(sector, count, buffer, false);
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if (rc) rc = ata_rw_sectors_internal(sector, count, buffer, false);
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ata_last_phys = sector + count - 1;
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ata_last_offset = 0;
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if (IS_ERR(rc))
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cprintf(CONSOLE_BOOT, "ATA: Error %08X while reading BBT (sector %d, count %d)\n",
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rc, sector, count);
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return rc;
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}
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#endif
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static struct ata_target_driverinfo drvinfo =
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{
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.set_retries = ata_set_retries,
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.srst_after_error = ata_srst_after_error,
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#ifdef ATA_HAVE_BBT
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.bbt_translate = ata_bbt_translate,
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.bbt_reload = ata_bbt_reload,
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.bbt_disable = ata_bbt_disable,
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#endif
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};
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void ata_set_retries(int retries)
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{
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ata_retries = retries;
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}
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void ata_srst_after_error(bool enable)
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{
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ata_error_srst = enable;
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}
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static uint16_t ata_read_cbr(uint32_t volatile* reg)
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{
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while (!(ATA_PIO_READY & 2)) yield();
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uint32_t dummy = *reg;
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while (!(ATA_PIO_READY & 1)) yield();
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return ATA_PIO_RDATA;
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}
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static void ata_write_cbr(uint32_t volatile* reg, uint16_t data)
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{
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while (!(ATA_PIO_READY & 2)) yield();
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*reg = data;
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}
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static int ata_wait_for_not_bsy(long timeout)
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{
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long startusec = USEC_TIMER;
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while (true)
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{
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uint8_t csd = ata_read_cbr(&ATA_PIO_CSD);
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if (!(csd & BIT(7))) return 0;
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if (TIMEOUT_EXPIRED(startusec, timeout)) RET_ERR(0);
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}
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}
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static int ata_wait_for_rdy(long timeout)
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{
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long startusec = USEC_TIMER;
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PASS_RC(ata_wait_for_not_bsy(timeout), 1, 0);
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while (true)
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{
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uint8_t dad = ata_read_cbr(&ATA_PIO_DAD);
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if (dad & BIT(6)) return 0;
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if (TIMEOUT_EXPIRED(startusec, timeout)) RET_ERR(1);
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}
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}
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static int ata_wait_for_start_of_transfer(long timeout)
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{
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long startusec = USEC_TIMER;
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PASS_RC(ata_wait_for_not_bsy(timeout), 2, 0);
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while (true)
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{
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uint8_t dad = ata_read_cbr(&ATA_PIO_DAD);
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if (dad & BIT(0)) RET_ERR(1);
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if ((dad & (BIT(7) | BIT(3))) == BIT(3)) return 0;
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if (TIMEOUT_EXPIRED(startusec, timeout)) RET_ERR(2);
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}
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}
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static int ata_wait_for_end_of_transfer(long timeout)
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{
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PASS_RC(ata_wait_for_not_bsy(timeout), 2, 0);
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uint8_t dad = ata_read_cbr(&ATA_PIO_DAD);
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if (dad & BIT(0)) RET_ERR(1);
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if ((dad & (BIT(3) | BITRANGE(5, 7))) == BIT(6)) return 0;
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RET_ERR(2);
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}
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int mmc_dsta_check_command_success(bool disable_crc)
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{
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int rc = 0;
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uint32_t dsta = SDCI_DSTA;
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if (dsta & SDCI_DSTA_RESTOUTE) rc |= 1;
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if (dsta & SDCI_DSTA_RESENDE) rc |= 2;
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if (dsta & SDCI_DSTA_RESINDE) rc |= 4;
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if (!disable_crc)
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if (dsta & SDCI_DSTA_RESCRCE)
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rc |= 8;
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if (rc) RET_ERR(rc);
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return 0;
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}
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bool mmc_send_command(uint32_t cmd, uint32_t arg, uint32_t* result, int timeout)
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{
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long starttime = USEC_TIMER;
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while ((SDCI_STATE & SDCI_STATE_CMD_STATE_MASK) != SDCI_STATE_CMD_STATE_CMD_IDLE)
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{
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if (TIMEOUT_EXPIRED(starttime, timeout)) RET_ERR(0);
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yield();
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}
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SDCI_STAC = SDCI_STAC_CLR_CMDEND | SDCI_STAC_CLR_BIT_3
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| SDCI_STAC_CLR_RESEND | SDCI_STAC_CLR_DATEND
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| SDCI_STAC_CLR_DAT_CRCEND | SDCI_STAC_CLR_CRC_STAEND
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| SDCI_STAC_CLR_RESTOUTE | SDCI_STAC_CLR_RESENDE
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| SDCI_STAC_CLR_RESINDE | SDCI_STAC_CLR_RESCRCE
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| SDCI_STAC_CLR_WR_DATCRCE | SDCI_STAC_CLR_RD_DATCRCE
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| SDCI_STAC_CLR_RD_DATENDE0 | SDCI_STAC_CLR_RD_DATENDE1
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| SDCI_STAC_CLR_RD_DATENDE2 | SDCI_STAC_CLR_RD_DATENDE3
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| SDCI_STAC_CLR_RD_DATENDE4 | SDCI_STAC_CLR_RD_DATENDE5
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| SDCI_STAC_CLR_RD_DATENDE6 | SDCI_STAC_CLR_RD_DATENDE7;
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SDCI_ARGU = arg;
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SDCI_CMD = cmd;
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if (!(SDCI_DSTA & SDCI_DSTA_CMDRDY)) RET_ERR(1);
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SDCI_CMD = cmd | SDCI_CMD_CMDSTR;
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sleep(1000);
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while (!(SDCI_DSTA & SDCI_DSTA_CMDEND))
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{
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if (TIMEOUT_EXPIRED(starttime, timeout)) RET_ERR(2);
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yield();
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}
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if ((cmd & SDCI_CMD_RES_TYPE_MASK) != SDCI_CMD_RES_TYPE_NONE)
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{
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while (!(SDCI_DSTA & SDCI_DSTA_RESEND))
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{
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if (TIMEOUT_EXPIRED(starttime, timeout)) RET_ERR(3);
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yield();
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}
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if (cmd & SDCI_CMD_RES_BUSY)
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while (SDCI_DSTA & SDCI_DSTA_DAT_BUSY)
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{
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if (TIMEOUT_EXPIRED(starttime, CEATA_DAT_NONBUSY_TIMEOUT)) RET_ERR(4);
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yield();
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}
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}
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bool nocrc = (cmd & SDCI_CMD_RES_SIZE_MASK) == SDCI_CMD_RES_SIZE_136;
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PASS_RC(mmc_dsta_check_command_success(nocrc), 3, 5);
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if (result) *result = SDCI_RESP0;
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return 0;
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}
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int mmc_get_card_status(uint32_t* result)
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{
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return mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SEND_STATUS)
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| SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
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| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
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MMC_CMD_SEND_STATUS_RCA(CEATA_MMC_RCA), result, CEATA_COMMAND_TIMEOUT);
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}
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int mmc_init()
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{
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sleep(100000);
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PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_GO_IDLE_STATE)
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| SDCI_CMD_CMD_TYPE_BC | SDCI_CMD_RES_TYPE_NONE
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| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NID,
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0, NULL, CEATA_COMMAND_TIMEOUT), 3, 0);
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long startusec = USEC_TIMER;
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uint32_t result;
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do
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{
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if (TIMEOUT_EXPIRED(startusec, CEATA_POWERUP_TIMEOUT)) RET_ERR(1);
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sleep(1000);
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PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SEND_OP_COND)
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| SDCI_CMD_CMD_TYPE_BCR | SDCI_CMD_RES_TYPE_R3
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| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NID,
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MMC_CMD_SEND_OP_COND_OCR(MMC_OCR_270_360),
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NULL, CEATA_COMMAND_TIMEOUT), 3, 2);
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result = SDCI_RESP0;
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}
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while (!(result & MMC_OCR_POWER_UP_DONE));
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PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_ALL_SEND_CID)
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| SDCI_CMD_CMD_TYPE_BCR | SDCI_CMD_RES_TYPE_R2
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| SDCI_CMD_RES_SIZE_136 | SDCI_CMD_NCR_NID_NID,
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0, NULL, CEATA_COMMAND_TIMEOUT), 3, 3);
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PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SET_RELATIVE_ADDR)
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| SDCI_CMD_CMD_TYPE_BCR | SDCI_CMD_RES_TYPE_R1
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| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
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MMC_CMD_SET_RELATIVE_ADDR_RCA(CEATA_MMC_RCA),
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NULL, CEATA_COMMAND_TIMEOUT), 3, 4);
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PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SELECT_CARD)
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| SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
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| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
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MMC_CMD_SELECT_CARD_RCA(CEATA_MMC_RCA),
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NULL, CEATA_COMMAND_TIMEOUT), 3, 5);
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PASS_RC(mmc_get_card_status(&result), 3, 6);
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if ((result & MMC_STATUS_CURRENT_STATE_MASK) != MMC_STATUS_CURRENT_STATE_TRAN) RET_ERR(7);
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return 0;
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}
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int mmc_fastio_write(uint32_t addr, uint32_t data)
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{
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return mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_FAST_IO)
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| SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R4
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| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
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MMC_CMD_FAST_IO_RCA(CEATA_MMC_RCA) | MMC_CMD_FAST_IO_DIRECTION_WRITE
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| MMC_CMD_FAST_IO_ADDRESS(addr) | MMC_CMD_FAST_IO_DATA(data),
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NULL, CEATA_COMMAND_TIMEOUT);
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}
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int mmc_fastio_read(uint32_t addr, uint32_t* data)
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288 |
{
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289 |
return mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_FAST_IO)
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| SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R4
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| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
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MMC_CMD_FAST_IO_RCA(CEATA_MMC_RCA) | MMC_CMD_FAST_IO_DIRECTION_READ
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293 |
| MMC_CMD_FAST_IO_ADDRESS(addr), data, CEATA_COMMAND_TIMEOUT);
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294 |
}
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296 |
int ceata_soft_reset()
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297 |
{
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298 |
PASS_RC(mmc_fastio_write(6, 4), 2, 0);
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299 |
sleep(1000);
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300 |
PASS_RC(mmc_fastio_write(6, 0), 2, 1);
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301 |
sleep(10000);
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302 |
long startusec = USEC_TIMER;
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303 |
uint32_t status;
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304 |
do
|
|
|
305 |
{
|
|
|
306 |
PASS_RC(mmc_fastio_read(0xf, &status), 2, 2);
|
|
|
307 |
if (TIMEOUT_EXPIRED(startusec, CEATA_POWERUP_TIMEOUT)) RET_ERR(3);
|
|
|
308 |
sleep(1000);
|
|
|
309 |
}
|
|
|
310 |
while (status & 0x80);
|
|
|
311 |
return 0;
|
|
|
312 |
}
|
|
|
313 |
|
|
|
314 |
int mmc_dsta_check_data_success()
|
|
|
315 |
{
|
|
|
316 |
int rc = 0;
|
|
|
317 |
uint32_t dsta = SDCI_DSTA;
|
|
|
318 |
if (dsta & (SDCI_DSTA_WR_DATCRCE | SDCI_DSTA_RD_DATCRCE))
|
|
|
319 |
{
|
|
|
320 |
if (dsta & SDCI_DSTA_WR_DATCRCE) rc |= 1;
|
|
|
321 |
if (dsta & SDCI_DSTA_RD_DATCRCE) rc |= 2;
|
|
|
322 |
if ((dsta & SDCI_DSTA_WR_CRC_STATUS_MASK) == SDCI_DSTA_WR_CRC_STATUS_TXERR) rc |= 4;
|
|
|
323 |
else if ((dsta & SDCI_DSTA_WR_CRC_STATUS_MASK) == SDCI_DSTA_WR_CRC_STATUS_CARDERR) rc |= 8;
|
|
|
324 |
}
|
|
|
325 |
if (dsta & (SDCI_DSTA_RD_DATENDE0 | SDCI_DSTA_RD_DATENDE1 | SDCI_DSTA_RD_DATENDE2
|
|
|
326 |
| SDCI_DSTA_RD_DATENDE3 | SDCI_DSTA_RD_DATENDE4 | SDCI_DSTA_RD_DATENDE5
|
|
|
327 |
| SDCI_DSTA_RD_DATENDE6 | SDCI_DSTA_RD_DATENDE7))
|
|
|
328 |
rc |= 16;
|
|
|
329 |
if (rc) RET_ERR(rc);
|
|
|
330 |
return 0;
|
|
|
331 |
}
|
|
|
332 |
|
|
|
333 |
void mmc_discard_irq()
|
|
|
334 |
{
|
|
|
335 |
SDCI_IRQ = SDCI_IRQ_DAT_DONE_INT | SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT
|
|
|
336 |
| SDCI_IRQ_MASK_MASK_READ_WAIT_INT;
|
|
|
337 |
wakeup_wait(&mmc_wakeup, TIMEOUT_NONE);
|
|
|
338 |
}
|
|
|
339 |
|
|
|
340 |
int ceata_read_multiple_register(uint32_t addr, void* dest, uint32_t size)
|
|
|
341 |
{
|
|
|
342 |
if (size > 0x10) RET_ERR(0);
|
|
|
343 |
mmc_discard_irq();
|
|
|
344 |
SDCI_DMASIZE = size;
|
|
|
345 |
SDCI_DMACOUNT = 1;
|
|
|
346 |
SDCI_DMAADDR = dest;
|
|
|
347 |
SDCI_DCTRL = SDCI_DCTRL_TXFIFORST | SDCI_DCTRL_RXFIFORST;
|
|
|
348 |
invalidate_dcache();
|
|
|
349 |
PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_REG)
|
|
|
350 |
| SDCI_CMD_CMD_TYPE_ADTC | SDCI_CMD_RES_TYPE_R1
|
|
|
351 |
| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
|
|
352 |
MMC_CMD_CEATA_RW_MULTIPLE_REG_DIRECTION_READ
|
|
|
353 |
| MMC_CMD_CEATA_RW_MULTIPLE_REG_ADDRESS(addr & 0xfc)
|
|
|
354 |
| MMC_CMD_CEATA_RW_MULTIPLE_REG_COUNT(size & 0xfc),
|
|
|
355 |
NULL, CEATA_COMMAND_TIMEOUT), 2, 1);
|
|
|
356 |
if (wakeup_wait(&mmc_wakeup, CEATA_COMMAND_TIMEOUT) == THREAD_TIMEOUT) RET_ERR(2);
|
|
|
357 |
PASS_RC(mmc_dsta_check_data_success(), 2, 3);
|
|
|
358 |
return 0;
|
|
|
359 |
}
|
|
|
360 |
|
|
|
361 |
int ceata_write_multiple_register(uint32_t addr, void* dest, uint32_t size)
|
|
|
362 |
{
|
|
|
363 |
int i;
|
|
|
364 |
if (size > 0x10) RET_ERR(0);
|
|
|
365 |
mmc_discard_irq();
|
|
|
366 |
SDCI_DMASIZE = size;
|
|
|
367 |
SDCI_DMACOUNT = 0;
|
|
|
368 |
SDCI_DCTRL = SDCI_DCTRL_TXFIFORST | SDCI_DCTRL_RXFIFORST;
|
|
|
369 |
PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_REG)
|
|
|
370 |
| SDCI_CMD_CMD_TYPE_ADTC | SDCI_CMD_CMD_RD_WR
|
|
|
371 |
| SDCI_CMD_RES_BUSY | SDCI_CMD_RES_TYPE_R1
|
|
|
372 |
| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
|
|
373 |
MMC_CMD_CEATA_RW_MULTIPLE_REG_DIRECTION_WRITE
|
|
|
374 |
| MMC_CMD_CEATA_RW_MULTIPLE_REG_ADDRESS(addr & 0xfc)
|
|
|
375 |
| MMC_CMD_CEATA_RW_MULTIPLE_REG_COUNT(size & 0xfc),
|
|
|
376 |
NULL, CEATA_COMMAND_TIMEOUT), 3, 1);
|
|
|
377 |
SDCI_DCTRL = SDCI_DCTRL_TRCONT_TX;
|
|
|
378 |
for (i = 0; i < size / 4; i++) SDCI_DATA = ((uint32_t*)dest)[i];
|
|
|
379 |
long startusec = USEC_TIMER;
|
|
|
380 |
if (wakeup_wait(&mmc_wakeup, CEATA_COMMAND_TIMEOUT) == THREAD_TIMEOUT) RET_ERR(2);
|
|
|
381 |
while ((SDCI_STATE & SDCI_STATE_DAT_STATE_MASK) != SDCI_STATE_DAT_STATE_IDLE)
|
|
|
382 |
{
|
|
|
383 |
if (TIMEOUT_EXPIRED(startusec, CEATA_COMMAND_TIMEOUT)) RET_ERR(3);
|
|
|
384 |
yield();
|
|
|
385 |
}
|
|
|
386 |
PASS_RC(mmc_dsta_check_data_success(), 3, 4);
|
|
|
387 |
return 0;
|
|
|
388 |
}
|
|
|
389 |
|
|
|
390 |
int ceata_init(int buswidth)
|
|
|
391 |
{
|
|
|
392 |
uint32_t result;
|
|
|
393 |
PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SWITCH) | SDCI_CMD_RES_BUSY
|
|
|
394 |
| SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
|
|
|
395 |
| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
|
|
396 |
MMC_CMD_SWITCH_ACCESS_WRITE_BYTE
|
|
|
397 |
| MMC_CMD_SWITCH_INDEX(MMC_CMD_SWITCH_FIELD_HS_TIMING)
|
|
|
398 |
| MMC_CMD_SWITCH_VALUE(MMC_CMD_SWITCH_FIELD_HS_TIMING_HIGH_SPEED),
|
|
|
399 |
&result, CEATA_COMMAND_TIMEOUT), 3, 0);
|
|
|
400 |
if (result & MMC_STATUS_SWITCH_ERROR) RET_ERR(1);
|
|
|
401 |
if (buswidth > 1)
|
|
|
402 |
{
|
|
|
403 |
int setting;
|
|
|
404 |
if (buswidth == 4) setting = MMC_CMD_SWITCH_FIELD_BUS_WIDTH_4BIT;
|
|
|
405 |
else if (buswidth == 8) setting = MMC_CMD_SWITCH_FIELD_BUS_WIDTH_8BIT;
|
|
|
406 |
else setting = MMC_CMD_SWITCH_FIELD_BUS_WIDTH_1BIT;
|
|
|
407 |
PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SWITCH) | SDCI_CMD_RES_BUSY
|
|
|
408 |
| SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
|
|
|
409 |
| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
|
|
410 |
MMC_CMD_SWITCH_ACCESS_WRITE_BYTE
|
|
|
411 |
| MMC_CMD_SWITCH_INDEX(MMC_CMD_SWITCH_FIELD_BUS_WIDTH)
|
|
|
412 |
| MMC_CMD_SWITCH_VALUE(setting),
|
|
|
413 |
&result, CEATA_COMMAND_TIMEOUT), 3, 2);
|
|
|
414 |
if (result & MMC_STATUS_SWITCH_ERROR) RET_ERR(3);
|
|
|
415 |
if (buswidth == 4)
|
|
|
416 |
SDCI_CTRL = (SDCI_CTRL & ~SDCI_CTRL_BUS_WIDTH_MASK) | SDCI_CTRL_BUS_WIDTH_4BIT;
|
|
|
417 |
else if (buswidth == 8)
|
|
|
418 |
SDCI_CTRL = (SDCI_CTRL & ~SDCI_CTRL_BUS_WIDTH_MASK) | SDCI_CTRL_BUS_WIDTH_8BIT;
|
|
|
419 |
}
|
|
|
420 |
PASS_RC(ceata_soft_reset(), 3, 4);
|
|
|
421 |
PASS_RC(ceata_read_multiple_register(0, ceata_taskfile, 0x10), 3, 5);
|
|
|
422 |
if (ceata_taskfile[0xc] != 0xce || ceata_taskfile[0xd] != 0xaa) RET_ERR(6);
|
|
|
423 |
PASS_RC(mmc_fastio_write(6, 0), 3, 7);
|
|
|
424 |
return 0;
|
|
|
425 |
}
|
|
|
426 |
|
|
|
427 |
int ceata_check_error()
|
|
|
428 |
{
|
|
|
429 |
uint32_t status, error;
|
|
|
430 |
PASS_RC(mmc_fastio_read(0xf, &status), 2, 0);
|
|
|
431 |
if (status & 1)
|
|
|
432 |
{
|
|
|
433 |
PASS_RC(mmc_fastio_read(0x9, &error), 2, 1);
|
|
|
434 |
RET_ERR((error << 2) | 2);
|
|
|
435 |
}
|
|
|
436 |
return 0;
|
|
|
437 |
}
|
|
|
438 |
|
|
|
439 |
int ceata_wait_idle()
|
|
|
440 |
{
|
|
|
441 |
long startusec = USEC_TIMER;
|
|
|
442 |
while (true)
|
|
|
443 |
{
|
|
|
444 |
uint32_t status;
|
|
|
445 |
PASS_RC(mmc_fastio_read(0xf, &status), 1, 0);
|
|
|
446 |
if (!(status & 0x88)) return 0;
|
|
|
447 |
if (TIMEOUT_EXPIRED(startusec, CEATA_DAT_NONBUSY_TIMEOUT)) RET_ERR(1);
|
|
|
448 |
sleep(50000);
|
|
|
449 |
}
|
|
|
450 |
}
|
|
|
451 |
|
|
|
452 |
int ceata_cancel_command()
|
|
|
453 |
{
|
|
|
454 |
*((uint32_t volatile*)0x3cf00200) = 0x9000e;
|
|
|
455 |
sleep(1);
|
|
|
456 |
*((uint32_t volatile*)0x3cf00200) = 0x9000f;
|
|
|
457 |
sleep(1);
|
|
|
458 |
*((uint32_t volatile*)0x3cf00200) = 0x90003;
|
|
|
459 |
sleep(1);
|
|
|
460 |
PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_STOP_TRANSMISSION)
|
|
|
461 |
| SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1 | SDCI_CMD_RES_BUSY
|
|
|
462 |
| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
|
|
463 |
0, NULL, CEATA_COMMAND_TIMEOUT), 1, 0);
|
|
|
464 |
PASS_RC(ceata_wait_idle(), 1, 1);
|
|
|
465 |
return 0;
|
|
|
466 |
}
|
|
|
467 |
|
|
|
468 |
int ceata_rw_multiple_block(bool write, void* buf, uint32_t count, long timeout)
|
|
|
469 |
{
|
|
|
470 |
mmc_discard_irq();
|
|
|
471 |
uint32_t responsetype;
|
|
|
472 |
uint32_t cmdtype;
|
|
|
473 |
uint32_t direction;
|
|
|
474 |
if (write)
|
|
|
475 |
{
|
|
|
476 |
cmdtype = SDCI_CMD_CMD_TYPE_ADTC | SDCI_CMD_CMD_RD_WR;
|
|
|
477 |
responsetype = SDCI_CMD_RES_TYPE_R1 | SDCI_CMD_RES_BUSY;
|
|
|
478 |
direction = MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_WRITE;
|
| 813 |
theseven |
479 |
clean_dcache();
|
| 643 |
theseven |
480 |
}
|
|
|
481 |
else
|
|
|
482 |
{
|
|
|
483 |
cmdtype = SDCI_CMD_CMD_TYPE_ADTC;
|
|
|
484 |
responsetype = SDCI_CMD_RES_TYPE_R1;
|
|
|
485 |
direction = MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_READ;
|
| 813 |
theseven |
486 |
invalidate_dcache();
|
| 643 |
theseven |
487 |
}
|
|
|
488 |
SDCI_DMASIZE = 0x200;
|
|
|
489 |
SDCI_DMAADDR = buf;
|
|
|
490 |
SDCI_DMACOUNT = count;
|
|
|
491 |
SDCI_DCTRL = SDCI_DCTRL_TXFIFORST | SDCI_DCTRL_RXFIFORST;
|
|
|
492 |
PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_BLOCK)
|
|
|
493 |
| SDCI_CMD_CMD_TYPE_ADTC | cmdtype | responsetype
|
|
|
494 |
| SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
|
|
495 |
direction | MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_COUNT(count),
|
| 965 |
theseven |
496 |
NULL, CEATA_COMMAND_TIMEOUT), 3, 0);
|
| 643 |
theseven |
497 |
if (write) SDCI_DCTRL = SDCI_DCTRL_TRCONT_TX;
|
|
|
498 |
if (wakeup_wait(&mmc_wakeup, timeout) == THREAD_TIMEOUT)
|
|
|
499 |
{
|
| 965 |
theseven |
500 |
PASS_RC(ceata_cancel_command(), 3, 1);
|
| 643 |
theseven |
501 |
RET_ERR(2);
|
|
|
502 |
}
|
| 965 |
theseven |
503 |
PASS_RC(mmc_dsta_check_data_success(), 3, 3);
|
| 643 |
theseven |
504 |
if (wakeup_wait(&mmc_comp_wakeup, timeout) == THREAD_TIMEOUT)
|
|
|
505 |
{
|
| 965 |
theseven |
506 |
PASS_RC(ceata_cancel_command(), 3, 4);
|
|
|
507 |
RET_ERR(5);
|
| 643 |
theseven |
508 |
}
|
| 965 |
theseven |
509 |
PASS_RC(ceata_check_error(), 3, 6);
|
| 643 |
theseven |
510 |
return 0;
|
|
|
511 |
}
|
|
|
512 |
|
|
|
513 |
int ata_identify(uint16_t* buf)
|
|
|
514 |
{
|
|
|
515 |
int i;
|
|
|
516 |
if (ceata)
|
|
|
517 |
{
|
|
|
518 |
memset(ceata_taskfile, 0, 16);
|
|
|
519 |
ceata_taskfile[0xf] = 0xec;
|
|
|
520 |
PASS_RC(ceata_wait_idle(), 2, 0);
|
|
|
521 |
PASS_RC(ceata_write_multiple_register(0, ceata_taskfile, 16), 2, 1);
|
|
|
522 |
PASS_RC(ceata_rw_multiple_block(false, buf, 1, CEATA_COMMAND_TIMEOUT), 2, 2);
|
|
|
523 |
}
|
|
|
524 |
else
|
|
|
525 |
{
|
|
|
526 |
PASS_RC(ata_wait_for_not_bsy(10000000), 1, 0);
|
|
|
527 |
ata_write_cbr(&ATA_PIO_DVR, 0);
|
|
|
528 |
ata_write_cbr(&ATA_PIO_CSD, 0xec);
|
|
|
529 |
PASS_RC(ata_wait_for_start_of_transfer(10000000), 1, 1);
|
| 836 |
theseven |
530 |
for (i = 0; i < 0x100; i++) buf[i] = ata_read_cbr(&ATA_PIO_DTR);
|
| 643 |
theseven |
531 |
}
|
|
|
532 |
return 0;
|
|
|
533 |
}
|
|
|
534 |
|
|
|
535 |
void ata_set_active(void)
|
|
|
536 |
{
|
|
|
537 |
ata_last_activity_value = USEC_TIMER;
|
|
|
538 |
}
|
|
|
539 |
|
|
|
540 |
bool ata_disk_is_active(void)
|
|
|
541 |
{
|
|
|
542 |
return ata_powered;
|
|
|
543 |
}
|
|
|
544 |
|
|
|
545 |
int ata_set_feature(uint32_t feature, uint32_t param)
|
|
|
546 |
{
|
| 965 |
theseven |
547 |
if (ceata)
|
|
|
548 |
{
|
|
|
549 |
memset(ceata_taskfile, 0, 16);
|
|
|
550 |
ceata_taskfile[0x1] = feature;
|
|
|
551 |
ceata_taskfile[0x2] = param;
|
|
|
552 |
ceata_taskfile[0xf] = 0xef;
|
|
|
553 |
PASS_RC(ceata_wait_idle(), 2, 0);
|
|
|
554 |
PASS_RC(ceata_write_multiple_register(0, ceata_taskfile, 16), 2, 1);
|
|
|
555 |
PASS_RC(ceata_wait_idle(), 2, 2);
|
|
|
556 |
}
|
|
|
557 |
else
|
|
|
558 |
{
|
|
|
559 |
PASS_RC(ata_wait_for_rdy(2000000), 2, 0);
|
|
|
560 |
ata_write_cbr(&ATA_PIO_DVR, 0);
|
|
|
561 |
ata_write_cbr(&ATA_PIO_FED, feature);
|
|
|
562 |
ata_write_cbr(&ATA_PIO_SCR, param);
|
|
|
563 |
ata_write_cbr(&ATA_PIO_CSD, 0xef);
|
|
|
564 |
PASS_RC(ata_wait_for_rdy(2000000), 2, 1);
|
|
|
565 |
}
|
| 643 |
theseven |
566 |
return 0;
|
|
|
567 |
}
|
|
|
568 |
|
|
|
569 |
int ata_power_up()
|
|
|
570 |
{
|
|
|
571 |
ata_set_active();
|
|
|
572 |
i2c_sendbyte(0, 0xe6, 0x1b, 1);
|
|
|
573 |
if (ceata)
|
|
|
574 |
{
|
| 965 |
theseven |
575 |
ata_lba48 = true;
|
|
|
576 |
ata_dma = true;
|
|
|
577 |
PCON(8) = 0x33333333;
|
|
|
578 |
PCON(9) = 0x00000033;
|
|
|
579 |
PCON(11) |= 0xf;
|
|
|
580 |
*((uint32_t volatile*)0x38a00000) = 0;
|
|
|
581 |
*((uint32_t volatile*)0x38700000) = 0;
|
| 643 |
theseven |
582 |
clockgate_enable(9, true);
|
|
|
583 |
SDCI_RESET = 0xa5;
|
|
|
584 |
sleep(1000);
|
|
|
585 |
*((uint32_t volatile*)0x3cf00380) = 0;
|
|
|
586 |
*((uint32_t volatile*)0x3cf0010c) = 0xff;
|
|
|
587 |
SDCI_CTRL = SDCI_CTRL_SDCIEN | SDCI_CTRL_CLK_SEL_SDCLK
|
|
|
588 |
| SDCI_CTRL_BIT_8 | SDCI_CTRL_BIT_14;
|
|
|
589 |
SDCI_CDIV = SDCI_CDIV_CLKDIV(260);
|
|
|
590 |
*((uint32_t volatile*)0x3cf00200) = 0xb000f;
|
|
|
591 |
SDCI_IRQ_MASK = SDCI_IRQ_MASK_MASK_DAT_DONE_INT | SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT;
|
| 965 |
theseven |
592 |
PASS_RC(mmc_init(), 3, 0);
|
| 643 |
theseven |
593 |
SDCI_CDIV = SDCI_CDIV_CLKDIV(4);
|
|
|
594 |
sleep(10000);
|
| 965 |
theseven |
595 |
PASS_RC(ceata_init(8), 3, 1);
|
|
|
596 |
PASS_RC(ata_identify(ata_identify_data), 3, 2);
|
| 643 |
theseven |
597 |
}
|
|
|
598 |
else
|
|
|
599 |
{
|
| 965 |
theseven |
600 |
PCON(7) = 0x44444444;
|
|
|
601 |
PCON(8) = 0x44444444;
|
|
|
602 |
PCON(9) = 0x44444444;
|
|
|
603 |
PCON(10) = (PCON(10) & ~0xffff) | 0x4444;
|
| 643 |
theseven |
604 |
clockgate_enable(5, true);
|
|
|
605 |
ATA_CFG = BIT(0);
|
| 965 |
theseven |
606 |
sleep(10000);
|
| 643 |
theseven |
607 |
ATA_CFG = 0;
|
|
|
608 |
sleep(6000);
|
|
|
609 |
ATA_SWRST = BIT(0);
|
|
|
610 |
sleep(500);
|
|
|
611 |
ATA_SWRST = 0;
|
|
|
612 |
sleep(90000);
|
|
|
613 |
ATA_CONTROL = BIT(0);
|
|
|
614 |
sleep(200000);
|
|
|
615 |
ATA_PIO_TIME = 0x191f7;
|
|
|
616 |
ATA_PIO_LHR = 0;
|
| 836 |
theseven |
617 |
ATA_CFG = BIT(6);
|
| 643 |
theseven |
618 |
while (!(ATA_PIO_READY & BIT(1))) sleep(100);
|
| 965 |
theseven |
619 |
PASS_RC(ata_identify(ata_identify_data), 3, 3);
|
| 643 |
theseven |
620 |
uint32_t piotime = 0x11f3;
|
|
|
621 |
uint32_t mdmatime = 0x1c175;
|
|
|
622 |
uint32_t udmatime = 0x5071152;
|
|
|
623 |
uint32_t param = 0;
|
|
|
624 |
ata_dma_flags = 0;
|
|
|
625 |
ata_lba48 = ata_identify_data[83] & BIT(10) ? true : false;
|
|
|
626 |
if (ata_identify_data[53] & BIT(1))
|
|
|
627 |
{
|
|
|
628 |
if (ata_identify_data[64] & BIT(1)) piotime = 0x2072;
|
|
|
629 |
else if (ata_identify_data[64] & BIT(0)) piotime = 0x7083;
|
|
|
630 |
}
|
|
|
631 |
if (ata_identify_data[63] & BIT(2))
|
|
|
632 |
{
|
|
|
633 |
mdmatime = 0x5072;
|
|
|
634 |
param = 0x22;
|
|
|
635 |
}
|
|
|
636 |
else if (ata_identify_data[63] & BIT(1))
|
|
|
637 |
{
|
|
|
638 |
mdmatime = 0x7083;
|
|
|
639 |
param = 0x21;
|
|
|
640 |
}
|
|
|
641 |
if (ata_identify_data[63] & BITRANGE(0, 2))
|
|
|
642 |
{
|
|
|
643 |
ata_dma_flags = BIT(3) | BIT(10);
|
|
|
644 |
param |= 0x20;
|
|
|
645 |
}
|
|
|
646 |
if (ata_identify_data[53] & BIT(2))
|
|
|
647 |
{
|
|
|
648 |
if (ata_identify_data[88] & BIT(4))
|
|
|
649 |
{
|
|
|
650 |
udmatime = 0x2010a52;
|
|
|
651 |
param = 0x44;
|
|
|
652 |
}
|
|
|
653 |
else if (ata_identify_data[88] & BIT(3))
|
|
|
654 |
{
|
|
|
655 |
udmatime = 0x2020a52;
|
|
|
656 |
param = 0x43;
|
|
|
657 |
}
|
|
|
658 |
else if (ata_identify_data[88] & BIT(2))
|
|
|
659 |
{
|
|
|
660 |
udmatime = 0x3030a52;
|
|
|
661 |
param = 0x42;
|
|
|
662 |
}
|
|
|
663 |
else if (ata_identify_data[88] & BIT(1))
|
|
|
664 |
{
|
|
|
665 |
udmatime = 0x3050a52;
|
|
|
666 |
param = 0x41;
|
|
|
667 |
}
|
|
|
668 |
if (ata_identify_data[88] & BITRANGE(0, 4))
|
|
|
669 |
{
|
|
|
670 |
ata_dma_flags = BIT(2) | BIT(3) | BIT(9) | BIT(10);
|
|
|
671 |
param |= 0x40;
|
|
|
672 |
}
|
|
|
673 |
}
|
|
|
674 |
ata_dma = param ? true : false;
|
| 965 |
theseven |
675 |
PASS_RC(ata_set_feature(0x03, param), 3, 4);
|
| 643 |
theseven |
676 |
ATA_PIO_TIME = piotime;
|
|
|
677 |
ATA_MDMA_TIME = mdmatime;
|
|
|
678 |
ATA_UDMA_TIME = udmatime;
|
|
|
679 |
}
|
| 965 |
theseven |
680 |
if (ata_identify_data[82] & BIT(5))
|
|
|
681 |
PASS_RC(ata_set_feature(ata_bbt ? 0x82 : 0x02, 0), 3, 5);
|
|
|
682 |
if (ata_identify_data[82] & BIT(6)) PASS_RC(ata_set_feature(0xaa, 0), 3, 6);
|
| 643 |
theseven |
683 |
if (ata_lba48)
|
|
|
684 |
ata_total_sectors = ata_identify_data[100]
|
|
|
685 |
| (((uint64_t)ata_identify_data[101]) << 16)
|
|
|
686 |
| (((uint64_t)ata_identify_data[102]) << 32)
|
|
|
687 |
| (((uint64_t)ata_identify_data[103]) << 48);
|
|
|
688 |
else ata_total_sectors = ata_identify_data[60] | (((uint32_t)ata_identify_data[61]) << 16);
|
|
|
689 |
ata_total_sectors >>= 3;
|
|
|
690 |
ata_powered = true;
|
|
|
691 |
ata_set_active();
|
|
|
692 |
return 0;
|
|
|
693 |
}
|
|
|
694 |
|
|
|
695 |
void ata_power_down()
|
|
|
696 |
{
|
|
|
697 |
if (!ata_powered) return;
|
|
|
698 |
ata_powered = false;
|
|
|
699 |
if (ceata)
|
|
|
700 |
{
|
|
|
701 |
memset(ceata_taskfile, 0, 16);
|
|
|
702 |
ceata_taskfile[0xf] = 0xe0;
|
|
|
703 |
ceata_wait_idle();
|
|
|
704 |
ceata_write_multiple_register(0, ceata_taskfile, 16);
|
| 965 |
theseven |
705 |
ceata_wait_idle();
|
|
|
706 |
sleep(100000);
|
| 643 |
theseven |
707 |
clockgate_enable(9, false);
|
|
|
708 |
}
|
|
|
709 |
else
|
|
|
710 |
{
|
|
|
711 |
ata_wait_for_rdy(1000000);
|
|
|
712 |
ata_write_cbr(&ATA_PIO_DVR, 0);
|
|
|
713 |
ata_write_cbr(&ATA_PIO_CSD, 0xe0);
|
|
|
714 |
ata_wait_for_rdy(1000000);
|
|
|
715 |
sleep(30000);
|
|
|
716 |
ATA_CONTROL = 0;
|
|
|
717 |
while (!(ATA_CONTROL & BIT(1))) yield();
|
|
|
718 |
clockgate_enable(5, false);
|
|
|
719 |
}
|
| 965 |
theseven |
720 |
PCON(7) = 0;
|
|
|
721 |
PCON(8) = 0;
|
|
|
722 |
PCON(9) = 0;
|
|
|
723 |
PCON(10) &= ~0xffff;
|
|
|
724 |
PCON(11) &= ~0xf;
|
| 643 |
theseven |
725 |
i2c_sendbyte(0, 0xe6, 0x1b, 0);
|
|
|
726 |
}
|
|
|
727 |
|
|
|
728 |
int ata_rw_chunk(uint64_t sector, uint32_t cnt, void* buffer, bool write)
|
|
|
729 |
{
|
|
|
730 |
if (ceata)
|
|
|
731 |
{
|
|
|
732 |
memset(ceata_taskfile, 0, 16);
|
|
|
733 |
ceata_taskfile[0x2] = cnt >> 5;
|
|
|
734 |
ceata_taskfile[0x3] = sector >> 21;
|
|
|
735 |
ceata_taskfile[0x4] = sector >> 29;
|
|
|
736 |
ceata_taskfile[0x5] = sector >> 37;
|
|
|
737 |
ceata_taskfile[0xa] = cnt << 3;
|
|
|
738 |
ceata_taskfile[0xb] = sector << 3;
|
|
|
739 |
ceata_taskfile[0xc] = sector >> 5;
|
|
|
740 |
ceata_taskfile[0xd] = sector >> 13;
|
|
|
741 |
ceata_taskfile[0xf] = write ? 0x35 : 0x25;
|
|
|
742 |
PASS_RC(ceata_wait_idle(), 2, 0);
|
|
|
743 |
PASS_RC(ceata_write_multiple_register(0, ceata_taskfile, 16), 2, 1);
|
|
|
744 |
PASS_RC(ceata_rw_multiple_block(write, buffer, cnt << 3, CEATA_COMMAND_TIMEOUT), 2, 2);
|
|
|
745 |
}
|
|
|
746 |
else
|
|
|
747 |
{
|
|
|
748 |
PASS_RC(ata_wait_for_rdy(100000), 2, 0);
|
|
|
749 |
ata_write_cbr(&ATA_PIO_DVR, 0);
|
|
|
750 |
if (ata_lba48)
|
|
|
751 |
{
|
|
|
752 |
ata_write_cbr(&ATA_PIO_SCR, cnt >> 5);
|
|
|
753 |
ata_write_cbr(&ATA_PIO_SCR, (cnt << 3) & 0xff);
|
|
|
754 |
ata_write_cbr(&ATA_PIO_LHR, (sector >> 37) & 0xff);
|
|
|
755 |
ata_write_cbr(&ATA_PIO_LMR, (sector >> 29) & 0xff);
|
|
|
756 |
ata_write_cbr(&ATA_PIO_LLR, (sector >> 21) & 0xff);
|
|
|
757 |
ata_write_cbr(&ATA_PIO_LHR, (sector >> 13) & 0xff);
|
|
|
758 |
ata_write_cbr(&ATA_PIO_LMR, (sector >> 5) & 0xff);
|
|
|
759 |
ata_write_cbr(&ATA_PIO_LLR, (sector << 3) & 0xff);
|
|
|
760 |
ata_write_cbr(&ATA_PIO_DVR, BIT(6));
|
|
|
761 |
if (write) ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0x35 : 0x39);
|
|
|
762 |
else ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0x25 : 0x29);
|
|
|
763 |
}
|
|
|
764 |
else
|
|
|
765 |
{
|
|
|
766 |
ata_write_cbr(&ATA_PIO_SCR, (cnt << 3) & 0xff);
|
|
|
767 |
ata_write_cbr(&ATA_PIO_LHR, (sector >> 13) & 0xff);
|
|
|
768 |
ata_write_cbr(&ATA_PIO_LMR, (sector >> 5) & 0xff);
|
|
|
769 |
ata_write_cbr(&ATA_PIO_LLR, (sector << 3) & 0xff);
|
|
|
770 |
ata_write_cbr(&ATA_PIO_DVR, BIT(6) | ((sector >> 21) & 0xf));
|
|
|
771 |
if (write) ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0xca : 0x30);
|
|
|
772 |
else ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0xc8 : 0xc4);
|
|
|
773 |
}
|
|
|
774 |
if (ata_dma)
|
|
|
775 |
{
|
|
|
776 |
PASS_RC(ata_wait_for_start_of_transfer(500000), 2, 1);
|
|
|
777 |
if (write)
|
|
|
778 |
{
|
| 813 |
theseven |
779 |
clean_dcache();
|
| 643 |
theseven |
780 |
ATA_SBUF_START = buffer;
|
|
|
781 |
ATA_SBUF_SIZE = SECTOR_SIZE * cnt;
|
|
|
782 |
ATA_CFG |= BIT(4);
|
|
|
783 |
}
|
|
|
784 |
else
|
|
|
785 |
{
|
| 813 |
theseven |
786 |
invalidate_dcache();
|
| 643 |
theseven |
787 |
ATA_TBUF_START = buffer;
|
|
|
788 |
ATA_TBUF_SIZE = SECTOR_SIZE * cnt;
|
|
|
789 |
ATA_CFG &= ~BIT(4);
|
|
|
790 |
}
|
|
|
791 |
ATA_XFR_NUM = SECTOR_SIZE * cnt - 1;
|
|
|
792 |
ATA_CFG |= ata_dma_flags;
|
|
|
793 |
ATA_CFG &= ~(BIT(7) | BIT(8));
|
|
|
794 |
wakeup_wait(&ata_wakeup, TIMEOUT_NONE);
|
|
|
795 |
ATA_IRQ = BITRANGE(0, 4);
|
|
|
796 |
ATA_IRQ_MASK = BIT(0);
|
|
|
797 |
ATA_COMMAND = BIT(0);
|
|
|
798 |
if (wakeup_wait(&ata_wakeup, 500000) == THREAD_TIMEOUT)
|
|
|
799 |
{
|
|
|
800 |
ATA_COMMAND = BIT(1);
|
|
|
801 |
ATA_CFG &= ~(BITRANGE(2, 3) | BIT(12));
|
|
|
802 |
RET_ERR(2);
|
|
|
803 |
}
|
|
|
804 |
ATA_COMMAND = BIT(1);
|
|
|
805 |
ATA_CFG &= ~(BITRANGE(2, 3) | BIT(12));
|
|
|
806 |
}
|
|
|
807 |
else
|
|
|
808 |
{
|
|
|
809 |
cnt *= SECTOR_SIZE / 512;
|
|
|
810 |
while (cnt--)
|
|
|
811 |
{
|
|
|
812 |
int i;
|
|
|
813 |
PASS_RC(ata_wait_for_start_of_transfer(500000), 2, 1);
|
|
|
814 |
if (write)
|
|
|
815 |
for (i = 0; i < 256; i++)
|
|
|
816 |
ata_write_cbr(&ATA_PIO_DTR, ((uint16_t*)buffer)[i]);
|
|
|
817 |
else
|
|
|
818 |
for (i = 0; i < 256; i++)
|
|
|
819 |
((uint16_t*)buffer)[i] = ata_read_cbr(&ATA_PIO_DTR);
|
|
|
820 |
buffer += 512;
|
|
|
821 |
}
|
|
|
822 |
}
|
|
|
823 |
PASS_RC(ata_wait_for_end_of_transfer(100000), 2, 3);
|
|
|
824 |
}
|
|
|
825 |
return 0;
|
|
|
826 |
}
|
|
|
827 |
|
|
|
828 |
#ifdef ATA_HAVE_BBT
|
|
|
829 |
int ata_bbt_translate(uint64_t sector, uint32_t count, uint64_t* phys, uint32_t* physcount)
|
|
|
830 |
{
|
|
|
831 |
if (sector + count > ata_virtual_sectors) RET_ERR(0);
|
|
|
832 |
if (!ata_bbt)
|
|
|
833 |
{
|
|
|
834 |
*phys = sector;
|
|
|
835 |
*physcount = count;
|
|
|
836 |
return 0;
|
|
|
837 |
}
|
|
|
838 |
if (!count)
|
|
|
839 |
{
|
|
|
840 |
*phys = 0;
|
|
|
841 |
*physcount = 0;
|
|
|
842 |
return 0;
|
|
|
843 |
}
|
|
|
844 |
uint32_t offset;
|
|
|
845 |
uint32_t l0idx = sector >> 15;
|
|
|
846 |
uint32_t l0offs = sector & 0x7fff;
|
|
|
847 |
*physcount = MIN(count, 0x8000 - l0offs);
|
|
|
848 |
uint32_t l0data = ata_bbt[0][l0idx << 1];
|
|
|
849 |
uint32_t base = ata_bbt[0][(l0idx << 1) | 1] << 12;
|
|
|
850 |
if (l0data < 0x8000) offset = l0data + base;
|
|
|
851 |
else
|
|
|
852 |
{
|
|
|
853 |
uint32_t l1idx = (sector >> 10) & 0x1f;
|
|
|
854 |
uint32_t l1offs = sector & 0x3ff;
|
|
|
855 |
*physcount = MIN(count, 0x400 - l1offs);
|
|
|
856 |
uint32_t l1data = ata_bbt[l0data & 0x7fff][l1idx];
|
|
|
857 |
if (l1data < 0x8000) offset = l1data + base;
|
|
|
858 |
else
|
|
|
859 |
{
|
|
|
860 |
uint32_t l2idx = (sector >> 5) & 0x1f;
|
|
|
861 |
uint32_t l2offs = sector & 0x1f;
|
|
|
862 |
*physcount = MIN(count, 0x20 - l2offs);
|
|
|
863 |
uint32_t l2data = ata_bbt[l1data & 0x7fff][l2idx];
|
|
|
864 |
if (l2data < 0x8000) offset = l2data + base;
|
|
|
865 |
else
|
|
|
866 |
{
|
|
|
867 |
uint32_t l3idx = sector & 0x1f;
|
|
|
868 |
uint32_t l3data = ata_bbt[l2data & 0x7fff][l3idx];
|
| 650 |
theseven |
869 |
for (*physcount = 1; *physcount < count && l3idx + *physcount < 0x20; (*physcount)++)
|
| 643 |
theseven |
870 |
if (ata_bbt[l2data & 0x7fff][l3idx + *physcount] != l3data)
|
|
|
871 |
break;
|
|
|
872 |
offset = l3data + base;
|
|
|
873 |
}
|
|
|
874 |
}
|
|
|
875 |
}
|
|
|
876 |
*phys = sector + offset;
|
|
|
877 |
return 0;
|
|
|
878 |
}
|
|
|
879 |
#endif
|
|
|
880 |
|
|
|
881 |
int ata_rw_sectors(uint64_t sector, uint32_t count, void* buffer, bool write)
|
|
|
882 |
{
|
|
|
883 |
if (((uint32_t)buffer) & (CACHEALIGN_SIZE - 1))
|
|
|
884 |
panicf(PANIC_KILLTHREAD,
|
|
|
885 |
"ATA: Misaligned data buffer at %08X (sector %lu, count %lu)",
|
|
|
886 |
(unsigned int)buffer, (unsigned int)sector, count);
|
|
|
887 |
#ifdef ATA_HAVE_BBT
|
|
|
888 |
if (sector + count > ata_virtual_sectors) RET_ERR(0);
|
|
|
889 |
if (ata_bbt)
|
|
|
890 |
while (count)
|
|
|
891 |
{
|
|
|
892 |
uint64_t phys;
|
|
|
893 |
uint32_t cnt;
|
|
|
894 |
PASS_RC(ata_bbt_translate(sector, count, &phys, &cnt), 0, 0);
|
|
|
895 |
uint32_t offset = phys - sector;
|
| 965 |
theseven |
896 |
if (offset != ata_last_offset && phys - ata_last_phys < 64) ata_reset();
|
| 643 |
theseven |
897 |
ata_last_offset = offset;
|
|
|
898 |
ata_last_phys = phys + cnt;
|
|
|
899 |
PASS_RC(ata_rw_sectors_internal(phys, cnt, buffer, write), 0, 0);
|
|
|
900 |
buffer += cnt * SECTOR_SIZE;
|
|
|
901 |
sector += cnt;
|
|
|
902 |
count -= cnt;
|
|
|
903 |
}
|
|
|
904 |
else PASS_RC(ata_rw_sectors_internal(sector, count, buffer, write), 0, 0);
|
|
|
905 |
return 0;
|
|
|
906 |
}
|
|
|
907 |
|
|
|
908 |
int ata_rw_sectors_internal(uint64_t sector, uint32_t count, void* buffer, bool write)
|
|
|
909 |
{
|
|
|
910 |
#endif
|
|
|
911 |
if (sector + count > ata_total_sectors) RET_ERR(0);
|
| 920 |
theseven |
912 |
if (!ata_powered) PASS_RC(ata_power_up(), 2, 1);
|
| 643 |
theseven |
913 |
ata_set_active();
|
|
|
914 |
if (ata_dma && write) clean_dcache();
|
|
|
915 |
else if (ata_dma) invalidate_dcache();
|
|
|
916 |
if (!ceata) ATA_COMMAND = BIT(1);
|
|
|
917 |
while (count)
|
|
|
918 |
{
|
|
|
919 |
uint32_t cnt = MIN(ata_lba48 ? 8192 : 32, count);
|
|
|
920 |
int rc = -1;
|
|
|
921 |
rc = ata_rw_chunk(sector, cnt, buffer, write);
|
| 965 |
theseven |
922 |
if (rc && ata_error_srst) ata_reset();
|
| 643 |
theseven |
923 |
if (rc && ata_retries)
|
|
|
924 |
{
|
|
|
925 |
void* buf = buffer;
|
|
|
926 |
uint64_t sect;
|
|
|
927 |
for (sect = sector; sect < sector + cnt; sect++)
|
|
|
928 |
{
|
|
|
929 |
rc = -1;
|
|
|
930 |
int tries = ata_retries;
|
|
|
931 |
while (tries-- && rc)
|
|
|
932 |
{
|
|
|
933 |
rc = ata_rw_chunk(sect, 1, buf, write);
|
| 965 |
theseven |
934 |
if (rc && ata_error_srst) ata_reset();
|
| 643 |
theseven |
935 |
}
|
|
|
936 |
if (rc) break;
|
|
|
937 |
buf += SECTOR_SIZE;
|
|
|
938 |
}
|
|
|
939 |
}
|
| 920 |
theseven |
940 |
PASS_RC(rc, 2, 2);
|
| 643 |
theseven |
941 |
buffer += SECTOR_SIZE * cnt;
|
|
|
942 |
sector += cnt;
|
|
|
943 |
count -= cnt;
|
|
|
944 |
}
|
|
|
945 |
ata_set_active();
|
|
|
946 |
return 0;
|
|
|
947 |
}
|
|
|
948 |
|
| 835 |
theseven |
949 |
static void ata_thread(void* arg0, void* arg1, void* arg2, void* arg3)
|
| 643 |
theseven |
950 |
{
|
|
|
951 |
while (true)
|
|
|
952 |
{
|
|
|
953 |
mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
|
|
|
954 |
if (TIME_AFTER(USEC_TIMER, ata_last_activity_value + ata_sleep_timeout) && ata_powered)
|
|
|
955 |
ata_power_down();
|
|
|
956 |
mutex_unlock(&ata_mutex);
|
|
|
957 |
sleep(1000000);
|
|
|
958 |
}
|
|
|
959 |
}
|
|
|
960 |
|
|
|
961 |
/* API Functions */
|
|
|
962 |
int ata_soft_reset()
|
|
|
963 |
{
|
|
|
964 |
int rc;
|
|
|
965 |
mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
|
| 920 |
theseven |
966 |
if (!ata_powered) PASS_RC(ata_power_up(), 1, 0);
|
| 643 |
theseven |
967 |
ata_set_active();
|
|
|
968 |
if (ceata) rc = ceata_soft_reset();
|
|
|
969 |
else
|
|
|
970 |
{
|
|
|
971 |
ata_write_cbr(&ATA_PIO_DAD, BIT(1) | BIT(2));
|
|
|
972 |
sleep(10);
|
|
|
973 |
ata_write_cbr(&ATA_PIO_DAD, 0);
|
| 965 |
theseven |
974 |
rc = ata_wait_for_rdy(3000000);
|
| 643 |
theseven |
975 |
}
|
| 965 |
theseven |
976 |
ata_set_active();
|
|
|
977 |
mutex_unlock(&ata_mutex);
|
|
|
978 |
PASS_RC(rc, 1, 1);
|
|
|
979 |
return 0;
|
|
|
980 |
}
|
|
|
981 |
|
|
|
982 |
int ata_hard_reset()
|
|
|
983 |
{
|
|
|
984 |
mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
|
|
|
985 |
PASS_RC(ata_power_up(), 0, 0);
|
|
|
986 |
ata_set_active();
|
|
|
987 |
mutex_unlock(&ata_mutex);
|
|
|
988 |
return 0;
|
|
|
989 |
}
|
|
|
990 |
|
|
|
991 |
int ata_reset()
|
|
|
992 |
{
|
|
|
993 |
int rc;
|
|
|
994 |
mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
|
|
|
995 |
if (!ata_powered) PASS_RC(ata_power_up(), 2, 0);
|
|
|
996 |
ata_set_active();
|
|
|
997 |
rc = ata_soft_reset();
|
| 643 |
theseven |
998 |
if (IS_ERR(rc))
|
|
|
999 |
{
|
| 965 |
theseven |
1000 |
rc = ata_hard_reset();
|
|
|
1001 |
if (IS_ERR(rc))
|
|
|
1002 |
{
|
|
|
1003 |
rc = ERR_RC((rc << 2) | 1);
|
|
|
1004 |
ata_power_down();
|
|
|
1005 |
sleep(3000000);
|
|
|
1006 |
int rc2 = ata_power_up();
|
|
|
1007 |
if (IS_ERR(rc2)) rc = ERR_RC((rc << 2) | 2);
|
|
|
1008 |
}
|
|
|
1009 |
else rc = 1;
|
| 643 |
theseven |
1010 |
}
|
|
|
1011 |
ata_set_active();
|
|
|
1012 |
mutex_unlock(&ata_mutex);
|
| 965 |
theseven |
1013 |
return rc;
|
| 643 |
theseven |
1014 |
}
|
|
|
1015 |
|
|
|
1016 |
int ata_read_sectors(IF_MD2(int drive,) unsigned long start, int incount,
|
|
|
1017 |
void* inbuf)
|
|
|
1018 |
{
|
|
|
1019 |
mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
|
|
|
1020 |
int rc = ata_rw_sectors(start, incount, inbuf, false);
|
|
|
1021 |
mutex_unlock(&ata_mutex);
|
|
|
1022 |
return rc;
|
|
|
1023 |
}
|
|
|
1024 |
|
|
|
1025 |
int ata_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
|
|
|
1026 |
const void* outbuf)
|
|
|
1027 |
{
|
|
|
1028 |
mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
|
|
|
1029 |
int rc = ata_rw_sectors(start, count, (void*)((uint32_t)outbuf), true);
|
|
|
1030 |
mutex_unlock(&ata_mutex);
|
|
|
1031 |
return rc;
|
|
|
1032 |
}
|
|
|
1033 |
|
|
|
1034 |
void ata_spindown(int seconds)
|
|
|
1035 |
{
|
|
|
1036 |
ata_sleep_timeout = seconds * 1000000;
|
|
|
1037 |
}
|
|
|
1038 |
|
|
|
1039 |
void ata_sleep(void)
|
|
|
1040 |
{
|
| 646 |
theseven |
1041 |
ata_last_activity_value = USEC_TIMER - ata_sleep_timeout + 200000;
|
| 643 |
theseven |
1042 |
}
|
|
|
1043 |
|
|
|
1044 |
void ata_sleepnow(void)
|
|
|
1045 |
{
|
| 646 |
theseven |
1046 |
mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
|
|
|
1047 |
ata_power_down();
|
|
|
1048 |
mutex_unlock(&ata_mutex);
|
| 643 |
theseven |
1049 |
}
|
|
|
1050 |
|
|
|
1051 |
void ata_close(void)
|
|
|
1052 |
{
|
| 646 |
theseven |
1053 |
ata_sleepnow();
|
| 643 |
theseven |
1054 |
}
|
|
|
1055 |
|
|
|
1056 |
void ata_spin(void)
|
|
|
1057 |
{
|
| 646 |
theseven |
1058 |
ata_set_active();
|
| 643 |
theseven |
1059 |
}
|
|
|
1060 |
|
|
|
1061 |
void ata_get_info(IF_MD2(int drive,) struct storage_info *info)
|
|
|
1062 |
{
|
|
|
1063 |
(*info).sector_size = SECTOR_SIZE;
|
|
|
1064 |
#ifdef ATA_HAVE_BBT
|
|
|
1065 |
(*info).num_sectors = ata_virtual_sectors;
|
|
|
1066 |
#else
|
|
|
1067 |
(*info).num_sectors = ata_total_sectors;
|
|
|
1068 |
#endif
|
|
|
1069 |
(*info).vendor = "Apple";
|
|
|
1070 |
(*info).product = "iPod Classic";
|
|
|
1071 |
(*info).revision = "1.0";
|
|
|
1072 |
(*info).driverinfo = &drvinfo;
|
|
|
1073 |
}
|
|
|
1074 |
|
|
|
1075 |
long ata_last_disk_activity(void)
|
|
|
1076 |
{
|
|
|
1077 |
return ata_last_activity_value;
|
|
|
1078 |
}
|
|
|
1079 |
|
|
|
1080 |
#ifdef ATA_HAVE_BBT
|
|
|
1081 |
void ata_bbt_disable()
|
|
|
1082 |
{
|
|
|
1083 |
mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
|
|
|
1084 |
if (ata_bbt) free(ata_bbt);
|
|
|
1085 |
ata_bbt = NULL;
|
|
|
1086 |
ata_virtual_sectors = ata_total_sectors;
|
|
|
1087 |
mutex_unlock(&ata_mutex);
|
|
|
1088 |
}
|
|
|
1089 |
|
| 920 |
theseven |
1090 |
int ata_bbt_reload()
|
| 643 |
theseven |
1091 |
{
|
|
|
1092 |
mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
|
|
|
1093 |
ata_bbt_disable();
|
| 965 |
theseven |
1094 |
PASS_RC(ata_power_up(), 1, 0);
|
| 643 |
theseven |
1095 |
uint32_t* buf = (uint32_t*)memalign(0x10, 0x1000);
|
|
|
1096 |
if (buf)
|
|
|
1097 |
{
|
|
|
1098 |
if (IS_ERR(ata_bbt_read_sectors(0, 1, buf)))
|
|
|
1099 |
ata_virtual_sectors = ata_total_sectors;
|
|
|
1100 |
else if (!memcmp(buf, "emBIbbth", 8))
|
|
|
1101 |
{
|
| 965 |
theseven |
1102 |
if (ata_identify_data[82] & BIT(5)) PASS_RC(ata_set_feature(0x02, 0), 1, 1);
|
| 643 |
theseven |
1103 |
ata_virtual_sectors = (((uint64_t)buf[0x1fd]) << 32) | buf[0x1fc];
|
|
|
1104 |
uint32_t count = buf[0x1ff];
|
|
|
1105 |
ata_bbt = (typeof(ata_bbt))memalign(0x10, 0x1000 * count);
|
|
|
1106 |
if (!ata_bbt)
|
|
|
1107 |
{
|
|
|
1108 |
cprintf(CONSOLE_BOOT, "ATA: Failed to allocate memory for BBT! (%d bytes)",
|
|
|
1109 |
0x1000 * count);
|
|
|
1110 |
ata_virtual_sectors = ata_total_sectors;
|
|
|
1111 |
}
|
|
|
1112 |
else
|
|
|
1113 |
{
|
|
|
1114 |
uint32_t i;
|
|
|
1115 |
uint32_t cnt;
|
|
|
1116 |
for (i = 0; i < count; i += cnt)
|
|
|
1117 |
{
|
|
|
1118 |
uint32_t phys = buf[0x200 + i];
|
|
|
1119 |
for (cnt = 1; cnt < count; cnt++)
|
|
|
1120 |
if (buf[0x200 + i + cnt] != phys + cnt)
|
|
|
1121 |
break;
|
|
|
1122 |
if (IS_ERR(ata_bbt_read_sectors(phys, cnt, ata_bbt[i << 6])))
|
|
|
1123 |
{
|
|
|
1124 |
free(ata_bbt);
|
|
|
1125 |
ata_virtual_sectors = ata_total_sectors;
|
|
|
1126 |
break;
|
|
|
1127 |
}
|
|
|
1128 |
}
|
| 814 |
theseven |
1129 |
if (ata_bbt) reownalloc(ata_bbt, KERNEL_OWNER(KERNEL_OWNER_ATA_BBT));
|
| 643 |
theseven |
1130 |
}
|
|
|
1131 |
}
|
|
|
1132 |
else ata_virtual_sectors = ata_total_sectors;
|
|
|
1133 |
free(buf);
|
|
|
1134 |
}
|
|
|
1135 |
else ata_virtual_sectors = ata_total_sectors;
|
|
|
1136 |
mutex_unlock(&ata_mutex);
|
| 965 |
theseven |
1137 |
return 0;
|
| 643 |
theseven |
1138 |
}
|
|
|
1139 |
#endif
|
|
|
1140 |
|
|
|
1141 |
int ata_init(void)
|
|
|
1142 |
{
|
|
|
1143 |
mutex_init(&ata_mutex);
|
|
|
1144 |
wakeup_init(&ata_wakeup);
|
|
|
1145 |
wakeup_init(&mmc_wakeup);
|
|
|
1146 |
wakeup_init(&mmc_comp_wakeup);
|
|
|
1147 |
ceata = PDAT(11) & BIT(1);
|
|
|
1148 |
ata_powered = false;
|
|
|
1149 |
ata_total_sectors = 0;
|
|
|
1150 |
#ifdef ATA_HAVE_BBT
|
| 920 |
theseven |
1151 |
PASS_RC(ata_bbt_reload(), 0, 0);
|
| 643 |
theseven |
1152 |
#endif
|
|
|
1153 |
thread_create(&ata_thread_handle, "ATA idle monitor", ata_thread, ata_stack,
|
| 835 |
theseven |
1154 |
sizeof(ata_stack), OS_THREAD, 1, true, NULL, NULL, NULL, NULL);
|
| 643 |
theseven |
1155 |
return 0;
|
|
|
1156 |
}
|
|
|
1157 |
|
|
|
1158 |
int ata_num_drives(int first_drive)
|
|
|
1159 |
{
|
|
|
1160 |
/* We don't care which logical drive number(s) we have been assigned */
|
|
|
1161 |
(void)first_drive;
|
|
|
1162 |
|
|
|
1163 |
return 1;
|
|
|
1164 |
}
|
|
|
1165 |
|
|
|
1166 |
void INT_ATA()
|
|
|
1167 |
{
|
|
|
1168 |
uint32_t ata_irq = ATA_IRQ;
|
|
|
1169 |
ATA_IRQ = ata_irq;
|
|
|
1170 |
if (ata_irq & ATA_IRQ_MASK) wakeup_signal(&ata_wakeup);
|
|
|
1171 |
ATA_IRQ_MASK = 0;
|
|
|
1172 |
}
|
|
|
1173 |
|
|
|
1174 |
void INT_MMC()
|
|
|
1175 |
{
|
|
|
1176 |
uint32_t irq = SDCI_IRQ;
|
|
|
1177 |
if (irq & SDCI_IRQ_DAT_DONE_INT) wakeup_signal(&mmc_wakeup);
|
|
|
1178 |
if (irq & SDCI_IRQ_IOCARD_IRQ_INT) wakeup_signal(&mmc_comp_wakeup);
|
|
|
1179 |
SDCI_IRQ = irq;
|
|
|
1180 |
}
|