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Rev Author Line No. Line
98 theseven 1 
ENTRY(__start)
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OUTPUT_FORMAT(elf32-littlearm)
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OUTPUT_ARCH(arm)
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STARTUP(build/ipodnano4g/target/ipodnano4g/crt0.o)
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MEMORY
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{
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    INIT : ORIGIN = 0x08000000, LENGTH = 0x01f80000
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    SRAM : ORIGIN = 0x22000000, LENGTH = 0x00030000
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    SDRAM : ORIGIN = 0x09f80000, LENGTH = 0x00080000
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}
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SECTIONS
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{
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    .inithead :
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    {
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        _initheadstart = .;
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        _poolstart = .;
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	*(.inithead*)
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        . = ALIGN(0x4);
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        _initheadend = .;
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    } > INIT
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    .sram :
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    {
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        _sramstart = .;
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        KEEP(*(.intvect))
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        *(.intvect)
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        *(.icode*)
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        *(.irodata*)
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        *(.idata*)
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        . = ALIGN(0x4);
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        _sramend = .;
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    } > SRAM AT> INIT
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    _sramsource = LOADADDR(.sram);
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    .sdram :
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    {
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        _sdramstart = .;
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        _poolend = .;
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        *(.text*)
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        *(.glue_7)
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        *(.glue_7t)
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        . = ALIGN(0x4);
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        *(.rodata*)
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        . = ALIGN(0x4);
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        *(.data*)
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        . = ALIGN(0x4);
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        _sdramend = .;
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    } > SDRAM AT> INIT
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    _sdramsource = LOADADDR(.sdram);
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    .init :
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    {
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        _initstart = .;
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        *(.initcode*)
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        *(.initrodata*)
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        *(.initdata*)
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        *(.inittail*)
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        . = ALIGN(0x4);
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        _initend = .;
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    } > INIT
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    .ibss (NOLOAD) :
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    {
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        _ibssstart = .;
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        *(.ibss*)
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        . = ALIGN(0x4);
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        _irqstackstart = .;
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        . += 0x400;
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        _irqstackend = .;
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        _abortstackstart = .;
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        . += 0x400;
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        _abortstackend = .;
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        *(.stack*)
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        . = ALIGN(0x4);
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        _ibssend = .;
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    } > SRAM
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    .bss (NOLOAD) :
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    {
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        _bssstart = .;
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        *(.bss*)
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        *(COMMON)
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        . = ALIGN(0x4);
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        _bssend = .;
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    } > SDRAM
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    /DISCARD/ :
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    {
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        *(.eh_frame)
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    }
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}