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@    Copyright 2010 TheSeven
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@    This file is part of emCORE.
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@
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@    emCORE is free software: you can redistribute it and/or
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@    modify it under the terms of the GNU General Public License as
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@    published by the Free Software Foundation, either version 2 of the
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@    License, or (at your option) any later version.
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@
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@    emCORE is distributed in the hope that it will be useful,
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@    but WITHOUT ANY WARRANTY; without even the implied warranty of
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@    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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@    See the GNU General Public License for more details.
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@
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@    You should have received a copy of the GNU General Public License
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@    along with emCORE.  If not, see <http://www.gnu.org/licenses/>.
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@
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@
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.section .intvect,"ax",%progbits
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	ldr pc, =reset_handler
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	ldr pc, =undef_instr_handler
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	ldr pc, =syscall_handler
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	ldr pc, =prefetch_abort_handler
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	ldr pc, =data_abort_handler
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	ldr pc, =reserved_handler
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	ldr pc, =irq_handler
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	ldr pc, =fiq_handler
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.ltorg
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98 theseven 36
.section .inithead,"ax",%progbits
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.global __start
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__start:
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	b	_start
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10 theseven 41
.section .initcode,"ax",%progbits
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.global _start
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_start:
85 theseven 44
	ldr	r0, =0x00450878
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	mcr	p15, 0, r0,c1,c0,0
10 theseven 46
	ldr	r0, =_sramsource
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	ldr	r1, =_sramstart
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	ldr	r2, =_sramend
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.copysram:
50
	cmp	r2, r1
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	ldrhi	r3, [r0], #4
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	strhi	r3, [r1], #4
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	bhi	.copysram
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	ldr	r0, =_sdramsource
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	ldr	r1, =_sdramstart
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	ldr	r2, =_sdramend
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.copysdram:
58
	cmp	r2, r1
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	ldrhi	r3, [r0], #4
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	strhi	r3, [r1], #4
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	bhi	.copysdram
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	ldr	r0, =_ibssstart
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	ldr	r1, =_ibssend
437 theseven 64
	mov	r2, #0
10 theseven 65
.clearibss:
66
	cmp	r1, r0
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	strhi	r2, [r0], #4
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	bhi	.clearibss
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	ldr	r0, =_bssstart
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	ldr	r1, =_bssend
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.clearbss:
72
	cmp	r1, r0
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	strhi	r2, [r0], #4
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	bhi	.clearbss
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	ldr	r1, =0x38200000
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	ldr	r0, [r1]
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	orr	r0, r0, #1
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	bic	r0, r0, #0x10000
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	str	r0, [r1]
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	mov	r0, #0
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	mcr	p15, 0, r0,c7,c5,0
85 theseven 82
	add	r1, r1, #0x00c00000
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	add	r2, r1, #0x00001000
84
	add	r3, r1, #0x00002000
85
	sub	r4, r0, #1
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	str	r4, [r1,#0x14]
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	str	r4, [r2,#0x14]
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	str	r4, [r1,#0xf00]
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	str	r4, [r2,#0xf00]
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	str	r4, [r3,#0x08]
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	str	r4, [r3,#0x0c]
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	str	r0, [r1,#0x14]
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	str	r0, [r2,#0x14]
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	mov	r0, #0
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	ldr	r1, =0x3c500000
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	str	r0, [r1,#0x48]
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	str	r0, [r1,#0x4c]
10 theseven 98
	msr	cpsr_c, #0xd2
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	ldr	sp, =_irqstackend
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	msr	cpsr_c, #0xd7
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	ldr	sp, =_abortstackend
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	msr	cpsr_c, #0xdb
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	ldr	sp, =_abortstackend
85 theseven 104
	msr	cpsr_c, #0x1f
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	ldr	sp, =_abortstackend
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	bl	init
593 theseven 107
	bl	yield
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	mov	r0, #0
99 theseven 109
	ldr	pc, =idleloop
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.ltorg
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.section .icode, "ax", %progbits
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.align 2
99 theseven 115
idleloop:
116
	mcr	p15, 0, r0,c7,c0,4
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	b	idleloop
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10 theseven 119
.global reset
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.global hang
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.type reset, %function
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.type hang, %function
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reset:
124
	msr	cpsr_c, #0xd3
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	mov	r0, #0x100000
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	mov	r1, #0x3c800000
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	str	r0, [r1]
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hang:
85 theseven 129
	msr	cpsr_c, #0xd3
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	mcr	p15, 0, r0,c7,c0,4
10 theseven 131
	b	hang
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.size reset, .-reset
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.size hang, .-hang
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135
.type reset_handler, %function
136
reset_handler:
702 theseven 137
	stmfd	sp, {r10-r12}
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	mov	r10, sp
139
	mov	r11, lr
140
	mrs	r12, cpsr
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	msr	cpsr_c, #0xd7
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	sub	sp, sp, #0x44
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	stmia	sp!, {r0-r9}
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	sub	r0, r10, #0xc
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	ldmia	r0, {r0-r2}
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	mov	r3, r10
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	mov	r4, r11
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	mov	r5, r11
149
	mov	r6, r12
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	stmia	sp!, {r0-r6}
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	sub	sp, sp, #0x44
85 theseven 152
	mov	r0, #0
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	adr	r1, reset_text
702 theseven 154
	mov	r2, r11
10 theseven 155
	b	panic
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.size reset_handler, .-reset_handler
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158
.type undef_instr_handler, %function
159
undef_instr_handler:
702 theseven 160
	sub	sp, sp, #0x44
161
	stmia	sp!, {r0-r12}
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	sub	r2, lr, #4
163
	mrs	r3, spsr
164
	mrs	r4, cpsr
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	orr	r0, r3, #0xc0
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	msr	cpsr_c, r0
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	mov	r0, sp
168
	mov	r1, lr
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	msr	cpsr_c, r4
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	stmia	sp!, {r0-r3}
171
	sub	sp, sp, #0x44
85 theseven 172
	mov	r0, #0
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	adr	r1, undef_instr_text
702 theseven 174
	ldr	r3, [r2]
10 theseven 175
	b	panicf
176
.size undef_instr_handler, .-undef_instr_handler
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178
.type prefetch_abort_handler, %function
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prefetch_abort_handler:
702 theseven 180
	sub	sp, sp, #0x44
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	stmia	sp!, {r0-r12}
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	sub	r2, lr, #4
183
	mrs	r3, spsr
184
	mrs	r4, cpsr
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	orr	r0, r3, #0xc0
186
	msr	cpsr_c, r0
187
	mov	r0, sp
188
	mov	r1, lr
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	msr	cpsr_c, r4
190
	stmia	sp!, {r0-r3}
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	sub	sp, sp, #0x44
85 theseven 192
	mov	r0, #0
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	adr	r1, prefetch_abort_text
702 theseven 194
	mrc	p15, 0, r3,c5,c0,1
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	mov	r4, r3,lsr#4
196
	and	r4, r4, #0xf
197
	and	r5, r3, #0xf
198
	stmfd	sp!, {r4-r5}
10 theseven 199
	b	panicf
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.size prefetch_abort_handler, .-prefetch_abort_handler
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202
.type data_abort_handler, %function
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data_abort_handler:
702 theseven 204
	sub	sp, sp, #0x44
205
	stmia	sp!, {r0-r12}
206
	sub	r2, lr, #8
207
	mrs	r3, spsr
208
	mrs	r4, cpsr
209
	orr	r0, r3, #0xc0
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	msr	cpsr_c, r0
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	mov	r0, sp
212
	mov	r1, lr
213
	msr	cpsr_c, r4
214
	stmia	sp!, {r0-r3}
215
	sub	sp, sp, #0x44
85 theseven 216
	mov	r0, #0
217
	adr	r1, data_abort_text
702 theseven 218
	mrc	p15, 0, r3,c5,c0
219
	mov	r4, r3,lsr#4
220
	and	r4, r4, #0xf
221
	and	r5, r3, #0xf
222
	mrc	p15, 0, r6,c6,c0
223
	stmfd	sp!, {r4-r6}
10 theseven 224
	b	panicf
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.size data_abort_handler, .-data_abort_handler
226
 
227
.type reserved_handler, %function
228
reserved_handler:
702 theseven 229
	stmfd	sp, {r10-r12}
230
	mov	r10, sp
231
	mov	r11, lr
232
	mrs	r12, cpsr
233
	msr	cpsr_c, #0xd7
234
	sub	sp, sp, #0x44
235
	stmia	sp!, {r0-r9}
236
	sub	r0, r10, #0xc
237
	ldmia	r0, {r0-r2}
238
	mov	r3, r10
239
	mov	r4, r11
240
	mov	r5, r11
241
	mov	r6, r12
242
	stmia	sp!, {r0-r6}
243
	sub	sp, sp, #0x44
85 theseven 244
	mov	r0, #0
245
	adr	r1, reserved_text
702 theseven 246
	mov	r2, r11
10 theseven 247
	b	panic
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.size reserved_handler, .-reserved_handler
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250
.type fiq_handler, %function
251
fiq_handler:
85 theseven 252
	mov	r0, #2
253
	adr	r1, fiq_text
10 theseven 254
	b	panic
255
.size fiq_handler, .-fiq_handler
256
 
702 theseven 257
prefetch_abort_text:
258
	.ascii	"Prefetch abort at %08X!\nFSR: %08X (domain %d, fault %d)\0"
259
 
260
reset_text:
261
	.ascii	"Hit reset vector!\n(Last known PC: %08X)\0"
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10 theseven 263
undef_instr_text:
702 theseven 264
	.ascii	"Undefined instruction at %08X!\n(Opcode: %08X)\0"
10 theseven 265
 
266
data_abort_text:
702 theseven 267
	.ascii	"Data abort at %08X!\nFSR: %08X (domain %d, fault %d)\nAddress: %08X\0"
10 theseven 268
 
269
fiq_text:
270
	.ascii	"Unhandled FIQ!\0"
271
 
702 theseven 272
reserved_text:
273
	.ascii	"Hit reserved exception handler!\n(Last known PC: %08X)\0"
274
 
10 theseven 275
syscall_text:
276
	.ascii	"Unhandled syscall!\0"
85 theseven 277
 
278
 
279
.section .icode.usec_timer, "ax", %progbits
280
.align 2
111 theseven 281
.global read_native_timer
282
.type read_native_timer, %function
283
read_native_timer:
85 theseven 284
	ldr	r0, val_3c700000
285
	ldr	r1, [r0,#0x80]
286
	ldr	r0, [r0,#0x84]
287
	bx	lr
111 theseven 288
.size read_native_timer, .-read_native_timer
85 theseven 289
 
290
.global read_usec_timer
291
.type read_usec_timer, %function
292
read_usec_timer:
293
	ldr	r0, val_3c700000
294
	ldr	r1, [r0,#0x80]
295
	ldr	r0, [r0,#0x84]
296
	mov	r0, r0,lsr#5
297
	orr	r0, r0, r1,lsl#27
298
	add	r0, r0, r0,asr#2
299
	add	r0, r0, r0,asr#6
300
	bx	lr
301
.size read_usec_timer, .-read_usec_timer
302
 
303
val_3c700000:
304
	.word	0x3c700000