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@
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@    Copyright 2010 TheSeven
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@
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@
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@    This file is part of emCORE.
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@
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@    emCORE is free software: you can redistribute it and/or
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@    modify it under the terms of the GNU General Public License as
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@    published by the Free Software Foundation, either version 2 of the
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@    License, or (at your option) any later version.
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@
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@    emCORE is distributed in the hope that it will be useful,
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@    but WITHOUT ANY WARRANTY; without even the implied warranty of
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@    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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@    See the GNU General Public License for more details.
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@
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@    You should have received a copy of the GNU General Public License
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@    along with emCORE.  If not, see <http://www.gnu.org/licenses/>.
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@
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@
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.section .intvect,"ax",%progbits
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	ldr pc, =reset_handler
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	ldr pc, =undef_instr_handler
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	ldr pc, =syscall_handler
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	ldr pc, =prefetch_abort_handler
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	ldr pc, =data_abort_handler
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	ldr pc, =reserved_handler
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	ldr pc, =irq_handler
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	ldr pc, =fiq_handler
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.ltorg
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.section .inithead,"ax",%progbits
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.global __start
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__start:
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	b	_start
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.section .initcode,"ax",%progbits
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.global _start
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_start:
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	mrc	p15, 0, r0,c1,c0
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	orr	r0, r0, #5
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	mcr	p15, 0, r0,c1,c0
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	ldr	r0, =_sramsource
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	ldr	r1, =_sramstart
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	ldr	r2, =_sramend
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.copysram:
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	cmp	r2, r1
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	ldrhi	r3, [r0], #4
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	strhi	r3, [r1], #4
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	bhi	.copysram
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	ldr	r0, =_sdramsource
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	ldr	r1, =_sdramstart
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	ldr	r2, =_sdramend
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.copysdram:
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	cmp	r2, r1
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	ldrhi	r3, [r0], #4
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	strhi	r3, [r1], #4
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	bhi	.copysdram
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	ldr	r0, =_ibssstart
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	ldr	r1, =_ibssend
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	mov	r2, #0
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.clearibss:
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	cmp	r1, r0
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	strhi	r2, [r0], #4
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	bhi	.clearibss
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	ldr	r0, =_bssstart
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	ldr	r1, =_bssend
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.clearbss:
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	cmp	r1, r0
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	strhi	r2, [r0], #4
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	bhi	.clearbss
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	ldr	r1, =0x38200000
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	ldr	r0, [r1]
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	orr	r0, r0, #1
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	bic	r0, r0, #0x10000
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	str	r0, [r1]
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	mov	r0, #0
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.cleancache:
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        mcr	p15, 0, r0,c7,c10,2
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        add	r1, r0, #0x10
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        mcr	p15, 0, r1,c7,c10,2
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        add	r1, r1, #0x10
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        mcr	p15, 0, r1,c7,c10,2
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        add	r1, r1, #0x10
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        mcr	p15, 0, r1,c7,c10,2
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        adds	r0, r0, #0x04000000
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        bne	.cleancache
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        mcr	p15, 0, r0,c7,c10,4
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	mcr	p15, 0, r0,c7,c5,0
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	mov	r1, #0x39c00000
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	str	r0, [r1,#4]
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	str	r0, [r1,#8]
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	str	r0, [r1,#0x38]
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	str	r0, [r1,#0x20]
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	sub	r0, r0, #1
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	str	r0, [r1]
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	str	r0, [r1,#0x10]
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	str	r0, [r1,#0x1c]
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	msr	cpsr_c, #0xd2
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	ldr	sp, =_irqstackend
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	msr	cpsr_c, #0xd7
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	ldr	sp, =_abortstackend
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	msr	cpsr_c, #0xdb
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	ldr	sp, =_abortstackend
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	msr	cpsr_c, #0x1f
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	ldr	sp, =_abortstackend
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	bl	init
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	bl	context_switch
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	mov	r0, #0
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	ldr	pc, =idleloop
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.ltorg
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.section .icode, "ax", %progbits
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.align 2
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idleloop:
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	mcr	p15, 0, r0,c7,c0,4
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	b	idleloop
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.global reset
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.global hang
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.type reset, %function
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.type hang, %function
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reset:
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	msr	cpsr_c, #0xd3
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	mov	r0, #0x110000
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	add	r0, r0, #0xff
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	add	r1, r0, #0xa00
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	mov	r2, #0x3c800000
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	str	r1, [r2]
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	mov	r1, #0xff0
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	str	r1, [r2,#4]
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	str	r0, [r2]
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hang:
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	msr	cpsr_c, #0xd3
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	mcr	p15, 0, r0,c7,c0,4
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	b	hang
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.size reset, .-reset
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.size hang, .-hang
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.type reset_handler, %function
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reset_handler:
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	mov	r0, #0
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	adr	r1, reset_text
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	b	panic
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reset_text:
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	.ascii	"Hit reset vector!\0"
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.size reset_handler, .-reset_handler
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.type undef_instr_handler, %function
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undef_instr_handler:
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	mov	r0, #0
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	adr	r1, undef_instr_text
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	sub	r2, lr, #4
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	b	panicf
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.size undef_instr_handler, .-undef_instr_handler
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.type prefetch_abort_handler, %function
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prefetch_abort_handler:
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	mov	r0, #0
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	adr	r1, prefetch_abort_text
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	sub	r2, lr, #4
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	b	panicf
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.size prefetch_abort_handler, .-prefetch_abort_handler
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.type data_abort_handler, %function
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data_abort_handler:
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	mov	r0, #0
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	adr	r1, data_abort_text
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	sub	r2, lr, #4
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	b	panicf
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.size data_abort_handler, .-data_abort_handler
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.type reserved_handler, %function
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reserved_handler:
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	mov	r0, #0
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	adr	r1, reserved_text
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	b	panic
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.size reserved_handler, .-reserved_handler
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.type fiq_handler, %function
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fiq_handler:
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	mov	r0, #2
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	adr	r1, fiq_text
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	b	panic
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.size fiq_handler, .-fiq_handler
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undef_instr_text:
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	.ascii	"Undefined instruction at %08X!\0"
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prefetch_abort_text:
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	.ascii	"Prefetch abort at %08X!\0"
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data_abort_text:
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	.ascii	"Data abort at %08X!\0"
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reserved_text:
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	.ascii	"Hit reserved exception handler!\0"
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fiq_text:
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	.ascii	"Unhandled FIQ!\0"
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syscall_text:
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	.ascii	"Unhandled syscall!\0"
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.section .icode.usec_timer, "ax", %progbits
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.align 2
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.global read_native_timer
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.type read_native_timer, %function
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read_native_timer:
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	ldr	r0, val_3c700000
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	ldr	r1, [r0,#0x80]
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	ldr	r0, [r0,#0x84]
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	bx	lr
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.size read_native_timer, .-read_native_timer
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.global read_usec_timer
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.type read_usec_timer, %function
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read_usec_timer:
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	ldr	r0, val_3c700000
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	ldr	r1, [r0,#0x80]
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	ldr	r0, [r0,#0x84]
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	add	r0, r0, r0,lsl#2
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	bx	lr
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.size read_usec_timer, .-read_usec_timer
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val_3c700000:
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	.word	0x3c700000
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.section .text.control_nor_cache, "ax", %progbits
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.align 2
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.global control_nor_cache
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.type control_nor_cache, %function
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control_nor_cache:
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	mrc	p15, 0, r3,c1,c0
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	bic	r1, r3, #1
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	mcr	p15, 0, r1,c1,c0
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	mov	r1, #0
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	mcr	p15, 0, r1,c7,c5
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cnc_flushcache_loop:
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	mcr	p15, 0, r1,c7,c14,2
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	add	r2, r1, #0x10
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	mcr	p15, 0, r2,c7,c14,2
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	add	r2, r2, #0x10
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	mcr	p15, 0, r2,c7,c14,2
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	add	r2, r2, #0x10
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	mcr	p15, 0, r2,c7,c14,2
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	adds	r1, r1, #0x04000000
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	bne	cnc_flushcache_loop
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	mcr	p15, 0, r1,c7,c10,4
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	ands	r0, r0, r0
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	mrc	p15, 0, r1,c2,c0, 1
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	biceq	r1, r1, #0x10
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	orrne	r1, r1, #0x10
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	mcr	p15, 0, r1,c2,c0, 1
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	mrc	p15, 0, r1,c2,c0, 0
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	biceq	r1, r1, #0x10
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	orrne	r1, r1, #0x10
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	mcr	p15, 0, r1,c2,c0, 0
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	mrc	p15, 0, r1,c3,c0, 0
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	biceq	r1, r1, #0x10
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	orrne	r1, r1, #0x10
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	mcr	p15, 0, r1,c3,c0, 0
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	mcr	p15, 0, r3,c1,c0
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	mov	pc, lr
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.size control_nor_cache, .-control_nor_cache