Subversion Repositories freemyipod

Rev

Go to most recent revision | Details | Last modification | View Log | RSS feed

Rev Author Line No. Line
2 theseven 1 
@
2 
@
3 
@    Copyright 2010 TheSeven
4 
@
5 
@
6 
@    This file is part of emBIOS.
7 
@
8 
@    emBIOS is free software: you can redistribute it and/or
9 
@    modify it under the terms of the GNU General Public License as
10 
@    published by the Free Software Foundation, either version 2 of the
11 
@    License, or (at your option) any later version.
12 
@
13 
@    emBIOS is distributed in the hope that it will be useful,
14 
@    but WITHOUT ANY WARRANTY; without even the implied warranty of
15 
@    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
16 
@    See the GNU General Public License for more details.
17 
@
18 
@    You should have received a copy of the GNU General Public License
19 
@    along with emBIOS.  If not, see <http://www.gnu.org/licenses/>.
20 
@
21 
@
22 
 
23 
 
24 
.section .intvect,"ax",%progbits
25 
	ldr pc, =reset_handler
26 
	ldr pc, =undef_instr_handler
27 
	ldr pc, =syscall_handler
28 
	ldr pc, =prefetch_abort_handler
29 
	ldr pc, =data_abort_handler
30 
	ldr pc, =reserved_handler
31 
	ldr pc, =irq_handler
32 
	ldr pc, =fiq_handler
33 
.ltorg
34 
 
35 
 
98 theseven 36 
.section .inithead,"ax",%progbits
37 
.global __start
38 
__start:
39 
	b	_start
40 
 
2 theseven 41 
.section .initcode,"ax",%progbits
42 
.global _start
43 
_start:
44 
	ldr	r0, =_sramsource
45 
	ldr	r1, =_sramstart
46 
	ldr	r2, =_sramend
47 
.copysram:
48 
	cmp	r2, r1
49 
	ldrhi	r3, [r0], #4
50 
	strhi	r3, [r1], #4
51 
	bhi	.copysram
52 
	ldr	r0, =_sdramsource
53 
	ldr	r1, =_sdramstart
54 
	ldr	r2, =_sdramend
55 
.copysdram:
56 
	cmp	r2, r1
57 
	ldrhi	r3, [r0], #4
58 
	strhi	r3, [r1], #4
59 
	bhi	.copysdram
60 
	ldr	r0, =_initbssstart
61 
	ldr	r1, =_initbssend
62 
	mov	r2, #0
63 
.clearinitbss:
64 
	cmp	r1, r0
65 
	strhi	r2, [r0], #4
66 
	bhi	.clearinitbss
67 
	ldr	r0, =_ibssstart
68 
	ldr	r1, =_ibssend
69 
.clearibss:
70 
	cmp	r1, r0
71 
	strhi	r2, [r0], #4
72 
	bhi	.clearibss
73 
	ldr	r0, =_bssstart
74 
	ldr	r1, =_bssend
75 
.clearbss:
76 
	cmp	r1, r0
77 
	strhi	r2, [r0], #4
78 
	bhi	.clearbss
79 
	ldr	r1, =0x38200000
80 
	ldr	r0, [r1]
81 
	orr	r0, r0, #1
82 
	bic	r0, r0, #0x10000
83 
	str	r0, [r1]
84 
	mov	r0, #0
85 
	mcr	p15, 0, r0,c7,c5,0
14 theseven 86 
	mov	r1, #0x39c00000
87 
	str	r0, [r1,#4]
88 
	str	r0, [r1,#8]
89 
	str	r0, [r1,#0x38]
90 
	str	r0, [r1,#0x20]
91 
	sub	r0, r0, #1
92 
	str	r0, [r1]
93 
	str	r0, [r1,#0x10]
94 
	str	r0, [r1,#0x1c]
2 theseven 95 
	msr	cpsr_c, #0xd2
96 
	ldr	sp, =_irqstackend
97 
	msr	cpsr_c, #0xd7
98 
	ldr	sp, =_abortstackend
99 
	msr	cpsr_c, #0xdb
100 
	ldr	sp, =_abortstackend
43 theseven 101 
	msr	cpsr_c, #0x1f
2 theseven 102 
	ldr	sp, =_initstackend
103 
	bl	init
15 theseven 104 
	bl	context_switch
14 theseven 105 
	mov	r0, #0
99 theseven 106 
	ldr	pc, =idleloop
2 theseven 107 
.ltorg
108 
 
109 
 
110 
.section .icode, "ax", %progbits
111 
.align 2
99 theseven 112 
idleloop:
113 
	mcr	p15, 0, r0,c7,c0,4
114 
	b	idleloop
115 
 
2 theseven 116 
.global reset
117 
.global hang
118 
.type reset, %function
119 
.type hang, %function
120 
reset:
121 
	msr	cpsr_c, #0xd3
122 
	mov	r0, #0x110000
123 
	add	r0, r0, #0xff
124 
	add	r1, r0, #0xa00
125 
	mov	r2, #0x3c800000
126 
	str	r1, [r2]
127 
	mov	r1, #0xff0
128 
	str	r1, [r2,#4]
129 
	str	r0, [r2]
130 
hang:
15 theseven 131 
	msr	cpsr_c, #0xd3
132 
	mcr	p15, 0, r0,c7,c0,4
2 theseven 133 
	b	hang
134 
.size reset, .-reset
135 
.size hang, .-hang
136 
 
137 
.type reset_handler, %function
138 
reset_handler:
43 theseven 139 
	mov	r0, #0
140 
	adr	r1, reset_text
2 theseven 141 
	b	panic
142 
reset_text:
143 
	.ascii	"Hit reset vector!\0"
144 
.size reset_handler, .-reset_handler
145 
 
146 
.type undef_instr_handler, %function
147 
undef_instr_handler:
43 theseven 148 
	mov	r0, #0
149 
	adr	r1, undef_instr_text
150 
	sub	r2, lr, #4
2 theseven 151 
	b	panicf
152 
.size undef_instr_handler, .-undef_instr_handler
153 
 
154 
.type prefetch_abort_handler, %function
155 
prefetch_abort_handler:
43 theseven 156 
	mov	r0, #0
157 
	adr	r1, prefetch_abort_text
158 
	sub	r2, lr, #4
2 theseven 159 
	b	panicf
160 
.size prefetch_abort_handler, .-prefetch_abort_handler
161 
 
162 
.type data_abort_handler, %function
163 
data_abort_handler:
43 theseven 164 
	mov	r0, #0
165 
	adr	r1, data_abort_text
166 
	sub	r2, lr, #4
2 theseven 167 
	b	panicf
168 
.size data_abort_handler, .-data_abort_handler
169 
 
170 
.type reserved_handler, %function
171 
reserved_handler:
43 theseven 172 
	mov	r0, #0
173 
	adr	r1, reserved_text
2 theseven 174 
	b	panic
175 
.size reserved_handler, .-reserved_handler
176 
 
177 
.type fiq_handler, %function
178 
fiq_handler:
43 theseven 179 
	mov	r0, #2
180 
	adr	r1, fiq_text
2 theseven 181 
	b	panic
182 
.size fiq_handler, .-fiq_handler
183 
 
184 
undef_instr_text:
185 
	.ascii	"Undefined instruction at %08X!\0"
186 
 
187 
prefetch_abort_text:
188 
	.ascii	"Prefetch abort at %08X!\0"
189 
 
190 
data_abort_text:
191 
	.ascii	"Data abort at %08X!\0"
192 
 
193 
reserved_text:
194 
	.ascii	"Hit reserved exception handler!\0"
195 
 
196 
fiq_text:
197 
	.ascii	"Unhandled FIQ!\0"
198 
 
199 
syscall_text:
200 
	.ascii	"Unhandled syscall!\0"
15 theseven 201 
 
202 
 
203 
.section .icode.usec_timer, "ax", %progbits
204 
.align 2
111 theseven 205 
.global read_native_timer
206 
.type read_native_timer, %function
207 
read_native_timer:
15 theseven 208 
	ldr	r0, val_3c700000
209 
	ldr	r1, [r0,#0x80]
210 
	ldr	r0, [r0,#0x84]
211 
	bx	lr
111 theseven 212 
.size read_native_timer, .-read_native_timer
15 theseven 213 
 
214 
.global read_usec_timer
215 
.type read_usec_timer, %function
216 
read_usec_timer:
217 
	ldr	r0, val_3c700000
218 
	ldr	r1, [r0,#0x80]
219 
	ldr	r0, [r0,#0x84]
220 
	add	r0, r0, r0,lsl#2
221 
	bx	lr
222 
.size read_usec_timer, .-read_usec_timer
223 
 
224 
val_3c700000:
225 
	.word	0x3c700000
95 theseven 226 
 
227 
 
228 
.section .text.control_nor_cache, "ax", %progbits
229 
.align 2
230 
.global control_nor_cache
231 
.type control_nor_cache, %function
232 
control_nor_cache:
233 
	mrc	p15, 0, r3,c1,c0
234 
	bic	r1, r3, #1
235 
	mcr	p15, 0, r1,c1,c0
236 
	mov	r1, #0
237 
	mcr	p15, 0, r1,c7,c5
238 
cnc_flushcache_loop:
239 
	mcr	p15, 0, r1,c7,c14,2
240 
	add	r2, r1, #0x10
241 
	mcr	p15, 0, r2,c7,c14,2
242 
	add	r2, r2, #0x10
243 
	mcr	p15, 0, r2,c7,c14,2
244 
	add	r2, r2, #0x10
245 
	mcr	p15, 0, r2,c7,c14,2
246 
	adds	r1, r1, #0x04000000
247 
	bne	cnc_flushcache_loop
248 
	mcr	p15, 0, r1,c7,c10,4
249 
	ands	r0, r0, r0
250 
	mrc	p15, 0, r1,c2,c0, 1
251 
	biceq	r1, r1, #0x10
252 
	orrne	r1, r1, #0x10
253 
	mcr	p15, 0, r1,c2,c0, 1
254 
	mrc	p15, 0, r1,c2,c0, 0
255 
	biceq	r1, r1, #0x10
256 
	orrne	r1, r1, #0x10
257 
	mcr	p15, 0, r1,c2,c0, 0
258 
	mrc	p15, 0, r1,c3,c0, 0
259 
	biceq	r1, r1, #0x10
260 
	orrne	r1, r1, #0x10
261 
	mcr	p15, 0, r1,c3,c0, 0
262 
	mcr	p15, 0, r3,c1,c0
263 
	mov	pc, lr
264 
.size control_nor_cache, .-control_nor_cache