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301 theseven 1 
/***************************************************************************
2 
 *             __________               __   ___.
3 
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
4 
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
5 
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
6 
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
7 
 *                     \/            \/     \/    \/            \/
8 
 * $Id$
9 
 *
10 
 * Copyright (C) 2007 Dave Chapman
11 
 *
12 
 * This program is free software; you can redistribute it and/or
13 
 * modify it under the terms of the GNU General Public License
14 
 * as published by the Free Software Foundation; either version 2
15 
 * of the License, or (at your option) any later version.
16 
 *
17 
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 
 * KIND, either express or implied.
19 
 *
20 
 ****************************************************************************/
21 
#include "global.h"
22 
#include "thread.h"
23 
#include "disk.h"
24 
#include "storage.h"
339 theseven 25 
#include "storage_ata-target.h"
301 theseven 26 
#include "timer.h"
629 theseven 27 
#include "constants/mmc.h"
301 theseven 28 
#include "../ipodnano3g/s5l8702.h"
29 
 
613 theseven 30 
 
31 
#ifndef ATA_RETRIES
32 
#define ATA_RETRIES 3
33 
#endif
34 
 
35 
 
629 theseven 36 
#define CEATA_POWERUP_TIMEOUT 30000000
37 
#define CEATA_COMMAND_TIMEOUT 1000000
38 
#define CEATA_DAT_NONBUSY_TIMEOUT 5000000
39 
#define CEATA_MMC_RCA 1
40 
 
41 
 
301 theseven 42 
/** static, private data **/
629 theseven 43 
static uint8_t ceata_taskfile[16] __attribute__((aligned(16)));
636 theseven 44 
uint16_t ata_identify_data[0x100] __attribute__((aligned(16)));
629 theseven 45 
bool ceata;
301 theseven 46 
bool ata_lba48;
47 
bool ata_dma;
48 
uint64_t ata_total_sectors;
601 theseven 49 
struct mutex ata_mutex;
301 theseven 50 
static struct wakeup ata_wakeup;
51 
static uint32_t ata_dma_flags;
52 
static long ata_last_activity_value = -1;
53 
static long ata_sleep_timeout = 20000000;
429 theseven 54 
static struct scheduler_thread ata_thread_handle;
55 
static uint32_t ata_stack[0x80] STACK_ATTR;
301 theseven 56 
static bool ata_powered;
620 theseven 57 
static int ata_retries = ATA_RETRIES;
58 
static bool ata_error_srst = true;
629 theseven 59 
static struct wakeup mmc_wakeup;
60 
static struct wakeup mmc_comp_wakeup;
301 theseven 61 
 
629 theseven 62 
 
328 theseven 63 
#ifdef ATA_HAVE_BBT
64 
#include "panic.h"
430 theseven 65 
uint16_t (*ata_bbt)[0x20];
339 theseven 66 
uint64_t ata_virtual_sectors;
337 theseven 67 
uint32_t ata_last_offset;
68 
uint64_t ata_last_phys;
301 theseven 69 
 
620 theseven 70 
int ata_bbt_read_sectors(uint32_t sector, uint32_t count, void* buffer)
328 theseven 71 
{
620 theseven 72 
    if (ata_last_phys != sector - 1 && ata_last_phys > sector - 64) ata_soft_reset();
328 theseven 73 
    int rc = ata_rw_sectors_internal(sector, count, buffer, false);
620 theseven 74 
    if (rc) rc = ata_rw_sectors_internal(sector, count, buffer, false);
75 
    ata_last_phys = sector + count - 1;
76 
    ata_last_offset = 0;
328 theseven 77 
    if (IS_ERR(rc))
620 theseven 78 
        cprintf(CONSOLE_BOOT, "ATA: Error %08X while reading BBT (sector %d, count %d)\n",
79 
                rc, sector, count);
80 
    return rc;
328 theseven 81 
}
82 
#endif
83 
 
613 theseven 84 
static struct ata_target_driverinfo drvinfo =
85 
{
620 theseven 86 
    .set_retries = ata_set_retries,
87 
    .srst_after_error = ata_srst_after_error,
613 theseven 88 
#ifdef ATA_HAVE_BBT
89 
    .bbt_translate = ata_bbt_translate,
90 
    .bbt_reload = ata_bbt_reload,
91 
    .bbt_disable = ata_bbt_disable
92 
#endif
93 
};
328 theseven 94 
 
613 theseven 95 
 
620 theseven 96 
void ata_set_retries(int retries)
97 
{
98 
    ata_retries = retries;
99 
}
100 
 
101 
void ata_srst_after_error(bool enable)
102 
{
103 
    ata_error_srst = enable;
104 
}
105 
 
301 theseven 106 
static uint16_t ata_read_cbr(uint32_t volatile* reg)
107 
{
317 theseven 108 
    while (!(ATA_PIO_READY & 2)) yield();
301 theseven 109 
    volatile uint32_t dummy = *reg;
317 theseven 110 
    while (!(ATA_PIO_READY & 1)) yield();
301 theseven 111 
    return ATA_PIO_RDATA;
112 
}
113 
 
114 
static void ata_write_cbr(uint32_t volatile* reg, uint16_t data)
115 
{
317 theseven 116 
    while (!(ATA_PIO_READY & 2)) yield();
301 theseven 117 
    *reg = data;
118 
}
119 
 
120 
static int ata_wait_for_not_bsy(long timeout)
121 
{
122 
    long startusec = USEC_TIMER;
123 
    while (true)
124 
    {
125 
        uint8_t csd = ata_read_cbr(&ATA_PIO_CSD);
126 
        if (!(csd & BIT(7))) return 0;
127 
        if (TIMEOUT_EXPIRED(startusec, timeout)) RET_ERR(0);
128 
    }
129 
}
130 
 
131 
static int ata_wait_for_rdy(long timeout)
132 
{
133 
    long startusec = USEC_TIMER;
134 
    PASS_RC(ata_wait_for_not_bsy(timeout), 1, 0);
135 
    while (true)
136 
    {
137 
        uint8_t dad = ata_read_cbr(&ATA_PIO_DAD);
138 
        if (dad & BIT(6)) return 0;
139 
        if (TIMEOUT_EXPIRED(startusec, timeout)) RET_ERR(1);
140 
    }
141 
}
142 
 
143 
static int ata_wait_for_start_of_transfer(long timeout)
144 
{
145 
    long startusec = USEC_TIMER;
146 
    PASS_RC(ata_wait_for_not_bsy(timeout), 2, 0);
147 
    while (true)
148 
    {
149 
        uint8_t dad = ata_read_cbr(&ATA_PIO_DAD);
150 
        if (dad & BIT(0)) RET_ERR(1);
151 
        if ((dad & (BIT(7) | BIT(3))) == BIT(3)) return 0;
152 
        if (TIMEOUT_EXPIRED(startusec, timeout)) RET_ERR(2);
153 
    }
154 
}
155 
 
156 
static int ata_wait_for_end_of_transfer(long timeout)
157 
{
158 
    PASS_RC(ata_wait_for_not_bsy(timeout), 2, 0);
159 
    uint8_t dad = ata_read_cbr(&ATA_PIO_DAD);
160 
    if (dad & BIT(0)) RET_ERR(1);
161 
    if ((dad & (BIT(3) | BITRANGE(5, 7))) == BIT(6)) return 0;
162 
    RET_ERR(2);
163 
}
164 
 
629 theseven 165 
int mmc_dsta_check_command_success(bool disable_crc)
166 
{
167 
    int rc = 0;
168 
    uint32_t dsta = SDCI_DSTA;
169 
    if (dsta & SDCI_DSTA_RESTOUTE) rc |= 1;
170 
    if (dsta & SDCI_DSTA_RESENDE) rc |= 2;
171 
    if (dsta & SDCI_DSTA_RESINDE) rc |= 4;
172 
    if (!disable_crc)
173 
        if (dsta & SDCI_DSTA_RESCRCE)
174 
            rc |= 8;
175 
    if (rc) RET_ERR(rc);
176 
    return 0;
177 
}
178 
 
179 
bool mmc_send_command(uint32_t cmd, uint32_t arg, uint32_t* result, int timeout)
180 
{
181 
    long starttime = USEC_TIMER;
182 
    while ((SDCI_STATE & SDCI_STATE_CMD_STATE_MASK) != SDCI_STATE_CMD_STATE_CMD_IDLE)
183 
    {
184 
        if (TIMEOUT_EXPIRED(starttime, timeout)) RET_ERR(0);
185 
        yield();
186 
    }
187 
    SDCI_STAC = SDCI_STAC_CLR_CMDEND | SDCI_STAC_CLR_BIT_3
188 
              | SDCI_STAC_CLR_RESEND | SDCI_STAC_CLR_DATEND
189 
              | SDCI_STAC_CLR_DAT_CRCEND | SDCI_STAC_CLR_CRC_STAEND
190 
              | SDCI_STAC_CLR_RESTOUTE | SDCI_STAC_CLR_RESENDE
191 
              | SDCI_STAC_CLR_RESINDE | SDCI_STAC_CLR_RESCRCE
192 
              | SDCI_STAC_CLR_WR_DATCRCE | SDCI_STAC_CLR_RD_DATCRCE
193 
              | SDCI_STAC_CLR_RD_DATENDE0 | SDCI_STAC_CLR_RD_DATENDE1
194 
              | SDCI_STAC_CLR_RD_DATENDE2 | SDCI_STAC_CLR_RD_DATENDE3
195 
              | SDCI_STAC_CLR_RD_DATENDE4 | SDCI_STAC_CLR_RD_DATENDE5
196 
              | SDCI_STAC_CLR_RD_DATENDE6 | SDCI_STAC_CLR_RD_DATENDE7;
197 
    SDCI_ARGU = arg;
198 
    SDCI_CMD = cmd;
199 
    if (!(SDCI_DSTA & SDCI_DSTA_CMDRDY)) RET_ERR(1);
200 
    SDCI_CMD = cmd | SDCI_CMD_CMDSTR;
201 
    sleep(1000);
202 
    while (!(SDCI_DSTA & SDCI_DSTA_CMDEND))
203 
    {
204 
        if (TIMEOUT_EXPIRED(starttime, timeout)) RET_ERR(2);
205 
        yield();
206 
    }
207 
    if ((cmd & SDCI_CMD_RES_TYPE_MASK) != SDCI_CMD_RES_TYPE_NONE)
208 
    {
209 
        while (!(SDCI_DSTA & SDCI_DSTA_RESEND))
210 
        {
211 
            if (TIMEOUT_EXPIRED(starttime, timeout)) RET_ERR(3);
212 
            yield();
213 
        }
214 
        if (cmd & SDCI_CMD_RES_BUSY)
215 
            while (SDCI_DSTA & SDCI_DSTA_DAT_BUSY)
216 
            {
217 
                if (TIMEOUT_EXPIRED(starttime, CEATA_DAT_NONBUSY_TIMEOUT)) RET_ERR(4);
218 
                yield();
219 
            }
220 
    }
221 
    bool nocrc = (cmd & SDCI_CMD_RES_SIZE_MASK) == SDCI_CMD_RES_SIZE_136;
222 
    PASS_RC(mmc_dsta_check_command_success(nocrc), 3, 5);
223 
    if (result) *result = SDCI_RESP0;
224 
    return 0;
225 
}
226 
 
227 
int mmc_get_card_status(uint32_t* result)
228 
{
229 
    return mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SEND_STATUS)
230 
                          | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
231 
                          | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
232 
                            MMC_CMD_SEND_STATUS_RCA(CEATA_MMC_RCA), result, CEATA_COMMAND_TIMEOUT);
233 
}
234 
 
235 
int mmc_init()
236 
{
237 
    sleep(100000);
238 
    PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_GO_IDLE_STATE)
239 
                           | SDCI_CMD_CMD_TYPE_BC | SDCI_CMD_RES_TYPE_NONE
240 
                           | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NID,
241 
                             0, NULL, CEATA_COMMAND_TIMEOUT), 3, 0);
242 
    long startusec = USEC_TIMER;
243 
    uint32_t result;
244 
    do
245 
    {
246 
        if (TIMEOUT_EXPIRED(startusec, CEATA_POWERUP_TIMEOUT)) RET_ERR(1);
247 
        sleep(1000);
248 
        PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SEND_OP_COND)
249 
                               | SDCI_CMD_CMD_TYPE_BCR | SDCI_CMD_RES_TYPE_R3
250 
                               | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NID,
251 
                                 MMC_CMD_SEND_OP_COND_OCR(MMC_OCR_270_360),
252 
                                 NULL, CEATA_COMMAND_TIMEOUT), 3, 2);
253 
        result = SDCI_RESP0;
254 
    }
255 
    while (!(result & MMC_OCR_POWER_UP_DONE));
256 
    PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_ALL_SEND_CID)
257 
                           | SDCI_CMD_CMD_TYPE_BCR | SDCI_CMD_RES_TYPE_R2
258 
                           | SDCI_CMD_RES_SIZE_136 | SDCI_CMD_NCR_NID_NID,
259 
                             0, NULL, CEATA_COMMAND_TIMEOUT), 3, 3);
260 
    PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SET_RELATIVE_ADDR)
261 
                           | SDCI_CMD_CMD_TYPE_BCR | SDCI_CMD_RES_TYPE_R1
262 
                           | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
263 
                             MMC_CMD_SET_RELATIVE_ADDR_RCA(CEATA_MMC_RCA),
264 
                             NULL, CEATA_COMMAND_TIMEOUT), 3, 4);
265 
    PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SELECT_CARD)
266 
                           | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
267 
                           | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
268 
                             MMC_CMD_SELECT_CARD_RCA(CEATA_MMC_RCA),
269 
                             NULL, CEATA_COMMAND_TIMEOUT), 3, 5);
270 
    PASS_RC(mmc_get_card_status(&result), 3, 6);
271 
    if ((result & MMC_STATUS_CURRENT_STATE_MASK) != MMC_STATUS_CURRENT_STATE_TRAN) RET_ERR(7);
272 
    return 0;
273 
}
274 
 
275 
int mmc_fastio_write(uint32_t addr, uint32_t data)
276 
{
277 
    return mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_FAST_IO)
278 
                          | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R4
279 
                          | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
280 
                            MMC_CMD_FAST_IO_RCA(CEATA_MMC_RCA) | MMC_CMD_FAST_IO_DIRECTION_WRITE
281 
                          | MMC_CMD_FAST_IO_ADDRESS(addr) | MMC_CMD_FAST_IO_DATA(data),
282 
                            NULL, CEATA_COMMAND_TIMEOUT);
283 
}
284 
 
285 
int mmc_fastio_read(uint32_t addr, uint32_t* data)
286 
{
287 
    return mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_FAST_IO)
288 
                          | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R4
289 
                          | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
290 
                            MMC_CMD_FAST_IO_RCA(CEATA_MMC_RCA) | MMC_CMD_FAST_IO_DIRECTION_READ
291 
                          | MMC_CMD_FAST_IO_ADDRESS(addr), data, CEATA_COMMAND_TIMEOUT);
292 
}
293 
 
294 
int ceata_soft_reset()
295 
{
296 
    PASS_RC(mmc_fastio_write(6, 4), 2, 0);
297 
    sleep(1000);
298 
    PASS_RC(mmc_fastio_write(6, 0), 2, 1);
299 
    sleep(10000);
300 
    long startusec = USEC_TIMER;
301 
    uint32_t status;
302 
    do
303 
    {
304 
        PASS_RC(mmc_fastio_read(0xf, &status), 2, 2);
305 
        if (TIMEOUT_EXPIRED(startusec, CEATA_POWERUP_TIMEOUT)) RET_ERR(3);
306 
        sleep(1000);
307 
    }
308 
    while (status & 0x80);
309 
    return 0;
310 
}
311 
 
312 
int mmc_dsta_check_data_success()
313 
{
314 
    int rc = 0;
315 
    uint32_t dsta = SDCI_DSTA;
316 
    if (dsta & (SDCI_DSTA_WR_DATCRCE | SDCI_DSTA_RD_DATCRCE))
317 
    {
318 
        if (dsta & SDCI_DSTA_WR_DATCRCE) rc |= 1;
319 
        if (dsta & SDCI_DSTA_RD_DATCRCE) rc |= 2;
320 
        if ((dsta & SDCI_DSTA_WR_CRC_STATUS_MASK) == SDCI_DSTA_WR_CRC_STATUS_TXERR) rc |= 4;
321 
        else if ((dsta & SDCI_DSTA_WR_CRC_STATUS_MASK) == SDCI_DSTA_WR_CRC_STATUS_CARDERR) rc |= 8;
322 
    }
323 
    if (dsta & (SDCI_DSTA_RD_DATENDE0 | SDCI_DSTA_RD_DATENDE1 | SDCI_DSTA_RD_DATENDE2
324 
              | SDCI_DSTA_RD_DATENDE3 | SDCI_DSTA_RD_DATENDE4 | SDCI_DSTA_RD_DATENDE5
325 
              | SDCI_DSTA_RD_DATENDE6 | SDCI_DSTA_RD_DATENDE7))
326 
        rc |= 16;
327 
    if (rc) RET_ERR(rc);
328 
    return 0;
329 
}
330 
 
331 
void mmc_discard_irq()
332 
{
333 
    SDCI_IRQ = SDCI_IRQ_DAT_DONE_INT | SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT
334 
             | SDCI_IRQ_MASK_MASK_READ_WAIT_INT;
335 
    wakeup_wait(&mmc_wakeup, TIMEOUT_NONE);
336 
}
337 
 
338 
int ceata_read_multiple_register(uint32_t addr, void* dest, uint32_t size)
339 
{
340 
    if (size > 0x10) RET_ERR(0);
341 
    mmc_discard_irq();
342 
    SDCI_DMASIZE = size;
343 
    SDCI_DMACOUNT = 1;
344 
    SDCI_DMAADDR = dest;
345 
    SDCI_DCTRL = SDCI_DCTRL_TXFIFORST | SDCI_DCTRL_RXFIFORST;
636 theseven 346 
    invalidate_dcache();
629 theseven 347 
    PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_REG)
348 
                           | SDCI_CMD_CMD_TYPE_ADTC | SDCI_CMD_RES_TYPE_R1
349 
                           | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
350 
                             MMC_CMD_CEATA_RW_MULTIPLE_REG_DIRECTION_READ
351 
                           | MMC_CMD_CEATA_RW_MULTIPLE_REG_ADDRESS(addr & 0xfc)
352 
                           | MMC_CMD_CEATA_RW_MULTIPLE_REG_COUNT(size & 0xfc),
353 
                             NULL, CEATA_COMMAND_TIMEOUT), 2, 1);
354 
    long startusec = USEC_TIMER;
355 
    if (wakeup_wait(&mmc_wakeup, CEATA_COMMAND_TIMEOUT) == THREAD_TIMEOUT) RET_ERR(2);
356 
    PASS_RC(mmc_dsta_check_data_success(), 2, 3);
357 
    return 0;
358 
}
359 
 
360 
int ceata_write_multiple_register(uint32_t addr, void* dest, uint32_t size)
361 
{
362 
    int i;
363 
    if (size > 0x10) RET_ERR(0);
364 
    mmc_discard_irq();
365 
    SDCI_DMASIZE = size;
366 
    SDCI_DMACOUNT = 0;
367 
    SDCI_DCTRL = SDCI_DCTRL_TXFIFORST | SDCI_DCTRL_RXFIFORST;
368 
    PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_REG)
369 
                           | SDCI_CMD_CMD_TYPE_ADTC | SDCI_CMD_CMD_RD_WR
370 
                           | SDCI_CMD_RES_BUSY | SDCI_CMD_RES_TYPE_R1
371 
                           | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
372 
                             MMC_CMD_CEATA_RW_MULTIPLE_REG_DIRECTION_WRITE
373 
                           | MMC_CMD_CEATA_RW_MULTIPLE_REG_ADDRESS(addr & 0xfc)
374 
                           | MMC_CMD_CEATA_RW_MULTIPLE_REG_COUNT(size & 0xfc),
375 
                             NULL, CEATA_COMMAND_TIMEOUT), 3, 1);
376 
    SDCI_DCTRL = SDCI_DCTRL_TRCONT_TX;
377 
    for (i = 0; i < size / 4; i++) SDCI_DATA = ((uint32_t*)dest)[i];
378 
    long startusec = USEC_TIMER;
379 
    if (wakeup_wait(&mmc_wakeup, CEATA_COMMAND_TIMEOUT) == THREAD_TIMEOUT) RET_ERR(2);
380 
    while ((SDCI_STATE & SDCI_STATE_DAT_STATE_MASK) != SDCI_STATE_DAT_STATE_IDLE)
381 
    {
382 
        if (TIMEOUT_EXPIRED(startusec, CEATA_COMMAND_TIMEOUT)) RET_ERR(3);
383 
        yield();
384 
    }
385 
    PASS_RC(mmc_dsta_check_data_success(), 3, 4);
386 
    return 0;
387 
}
388 
 
389 
int ceata_init(int buswidth)
390 
{
391 
    uint32_t result;
392 
    PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SWITCH) | SDCI_CMD_RES_BUSY
393 
                           | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
394 
                           | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
395 
                             MMC_CMD_SWITCH_ACCESS_WRITE_BYTE
396 
                           | MMC_CMD_SWITCH_INDEX(MMC_CMD_SWITCH_FIELD_HS_TIMING)
397 
                           | MMC_CMD_SWITCH_VALUE(MMC_CMD_SWITCH_FIELD_HS_TIMING_HIGH_SPEED),
398 
                             &result, CEATA_COMMAND_TIMEOUT), 3, 0);
399 
    if (result & MMC_STATUS_SWITCH_ERROR) RET_ERR(1);
400 
    if (buswidth > 1)
401 
    {
402 
        int setting;
403 
        if (buswidth == 4) setting = MMC_CMD_SWITCH_FIELD_BUS_WIDTH_4BIT;
404 
        else if (buswidth == 8) setting = MMC_CMD_SWITCH_FIELD_BUS_WIDTH_8BIT;
405 
        else setting = MMC_CMD_SWITCH_FIELD_BUS_WIDTH_1BIT;
406 
        PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SWITCH) | SDCI_CMD_RES_BUSY
407 
                               | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
408 
                               | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
409 
                                 MMC_CMD_SWITCH_ACCESS_WRITE_BYTE
410 
                               | MMC_CMD_SWITCH_INDEX(MMC_CMD_SWITCH_FIELD_BUS_WIDTH)
411 
                               | MMC_CMD_SWITCH_VALUE(setting),
412 
                                 &result, CEATA_COMMAND_TIMEOUT), 3, 2);
413 
        if (result & MMC_STATUS_SWITCH_ERROR) RET_ERR(3);
414 
        if (buswidth == 4)
415 
            SDCI_CTRL = (SDCI_CTRL & ~SDCI_CTRL_BUS_WIDTH_MASK) | SDCI_CTRL_BUS_WIDTH_4BIT;
416 
        else if (buswidth == 8)
417 
            SDCI_CTRL = (SDCI_CTRL & ~SDCI_CTRL_BUS_WIDTH_MASK) | SDCI_CTRL_BUS_WIDTH_8BIT;
418 
    }
419 
    PASS_RC(ceata_soft_reset(), 3, 4);
420 
    PASS_RC(ceata_read_multiple_register(0, ceata_taskfile, 0x10), 3, 5);
421 
    if (ceata_taskfile[0xc] != 0xce || ceata_taskfile[0xd] != 0xaa) RET_ERR(6);
422 
    PASS_RC(mmc_fastio_write(6, 0), 3, 7);
423 
    return 0;
424 
}
425 
 
426 
int ceata_check_error()
427 
{
428 
    uint32_t status, error;
429 
    PASS_RC(mmc_fastio_read(0xf, &status), 2, 0);
430 
    if (status & 1)
431 
    {
432 
        PASS_RC(mmc_fastio_read(0x9, &error), 2, 1);
433 
        RET_ERR((error << 2) | 2);
434 
    }
435 
    return 0;
436 
}
437 
 
438 
int ceata_wait_idle()
439 
{
440 
    long startusec = USEC_TIMER;
441 
    while (true)
442 
    {
443 
        uint32_t status;
444 
        PASS_RC(mmc_fastio_read(0xf, &status), 1, 0);
445 
        if (!(status & 0x88)) return 0;
446 
        if (TIMEOUT_EXPIRED(startusec, CEATA_DAT_NONBUSY_TIMEOUT)) RET_ERR(1);
447 
        sleep(50000);
448 
    }
449 
}
450 
 
451 
int ceata_cancel_command()
452 
{
453 
    *((uint32_t volatile*)0x3cf00200) = 0x9000e;
454 
    sleep(1);
455 
    *((uint32_t volatile*)0x3cf00200) = 0x9000f;
456 
    sleep(1);
457 
    *((uint32_t volatile*)0x3cf00200) = 0x90003;
458 
    sleep(1);
459 
    PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_STOP_TRANSMISSION)
460 
                           | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1 | SDCI_CMD_RES_BUSY
461 
                           | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
462 
                             0, NULL, CEATA_COMMAND_TIMEOUT), 1, 0);
463 
    PASS_RC(ceata_wait_idle(), 1, 1);
464 
    return 0;
465 
}
466 
 
467 
int ceata_rw_multiple_block(bool write, void* buf, uint32_t count, long timeout)
468 
{
469 
    mmc_discard_irq();
470 
    uint32_t responsetype;
471 
    uint32_t cmdtype;
472 
    uint32_t direction;
473 
    if (write)
474 
    {
475 
        cmdtype = SDCI_CMD_CMD_TYPE_ADTC | SDCI_CMD_CMD_RD_WR;
476 
        responsetype = SDCI_CMD_RES_TYPE_R1 | SDCI_CMD_RES_BUSY;
477 
        direction = MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_WRITE;
478 
    }
479 
    else
480 
    {
481 
        cmdtype = SDCI_CMD_CMD_TYPE_ADTC;
482 
        responsetype = SDCI_CMD_RES_TYPE_R1;
483 
        direction = MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_READ;
484 
    }
485 
    SDCI_DMASIZE = 0x200;
486 
    SDCI_DMAADDR = buf;
487 
    SDCI_DMACOUNT = count;
488 
    SDCI_DCTRL = SDCI_DCTRL_TXFIFORST | SDCI_DCTRL_RXFIFORST;
636 theseven 489 
    invalidate_dcache();
629 theseven 490 
    PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_BLOCK)
491 
                           | SDCI_CMD_CMD_TYPE_ADTC | cmdtype | responsetype
492 
                           | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
493 
                             direction | MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_COUNT(count),
494 
                             NULL, CEATA_COMMAND_TIMEOUT), 4, 0);
495 
    if (write) SDCI_DCTRL = SDCI_DCTRL_TRCONT_TX;
496 
    if (wakeup_wait(&mmc_wakeup, timeout) == THREAD_TIMEOUT)
497 
    {
498 
        PASS_RC(ceata_cancel_command(), 4, 1);
499 
        RET_ERR(2);
500 
    }
501 
    PASS_RC(mmc_dsta_check_data_success(), 4, 3);
502 
    if (wakeup_wait(&mmc_comp_wakeup, timeout) == THREAD_TIMEOUT)
503 
    {
504 
        PASS_RC(ceata_cancel_command(), 4, 4);
505 
        RET_ERR(4);
506 
    }
507 
    PASS_RC(ceata_check_error(), 4, 5);
508 
    return 0;
509 
}
510 
 
301 theseven 511 
int ata_identify(uint16_t* buf)
512 
{
513 
    int i;
629 theseven 514 
    if (ceata)
301 theseven 515 
    {
629 theseven 516 
        memset(ceata_taskfile, 0, 16);
517 
        ceata_taskfile[0xf] = 0xec;
518 
        PASS_RC(ceata_wait_idle(), 2, 0);
519 
        PASS_RC(ceata_write_multiple_register(0, ceata_taskfile, 16), 2, 1);
520 
        PASS_RC(ceata_rw_multiple_block(false, buf, 1, CEATA_COMMAND_TIMEOUT), 2, 2);
301 theseven 521 
    }
629 theseven 522 
    else
523 
    {
524 
        PASS_RC(ata_wait_for_not_bsy(10000000), 1, 0);
525 
        ata_write_cbr(&ATA_PIO_DVR, 0);
526 
        ata_write_cbr(&ATA_PIO_CSD, 0xec);
527 
        PASS_RC(ata_wait_for_start_of_transfer(10000000), 1, 1);
528 
        for (i = 0; i < 0x100; i++)
529 
        {
530 
            uint16_t word = ata_read_cbr(&ATA_PIO_DTR);
531 
            buf[i] = (word >> 8) | (word << 8);
532 
        }
533 
    }
534 
    return 0;
301 theseven 535 
}
536 
 
537 
void ata_set_active(void)
538 
{
539 
    ata_last_activity_value = USEC_TIMER;
540 
}
541 
 
620 theseven 542 
bool ata_disk_is_active(void)
543 
{
544 
    return ata_powered;
545 
}
546 
 
317 theseven 547 
int ata_set_feature(uint32_t feature, uint32_t param)
548 
{
549 
    PASS_RC(ata_wait_for_rdy(500000), 1, 0);
550 
    ata_write_cbr(&ATA_PIO_DVR, 0);
551 
    ata_write_cbr(&ATA_PIO_FED, 3);
552 
    ata_write_cbr(&ATA_PIO_SCR, param);
553 
    ata_write_cbr(&ATA_PIO_CSD, feature);
554 
    PASS_RC(ata_wait_for_rdy(500000), 1, 1);
555 
    return 0;
556 
}
557 
 
301 theseven 558 
int ata_power_up()
559 
{
560 
    ata_set_active();
357 theseven 561 
    if (ata_powered) return 0;
301 theseven 562 
    i2c_sendbyte(0, 0xe6, 0x1b, 1);
629 theseven 563 
    if (ceata)
301 theseven 564 
    {
629 theseven 565 
        clockgate_enable(9, true);
566 
        SDCI_RESET = 0xa5;
567 
        sleep(1000);
568 
        *((uint32_t volatile*)0x3cf00380) = 0;
569 
        *((uint32_t volatile*)0x3cf0010c) = 0xff;
570 
        SDCI_CTRL = SDCI_CTRL_SDCIEN | SDCI_CTRL_CLK_SEL_SDCLK
571 
                  | SDCI_CTRL_BIT_8 | SDCI_CTRL_BIT_14;
572 
        SDCI_CDIV = SDCI_CDIV_CLKDIV(260);
573 
        *((uint32_t volatile*)0x3cf00200) = 0xb000f;
574 
        SDCI_IRQ_MASK = SDCI_IRQ_MASK_MASK_DAT_DONE_INT | SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT;
575 
        PASS_RC(mmc_init(), 2, 0);
576 
        SDCI_CDIV = SDCI_CDIV_CLKDIV(4);
577 
        sleep(10000);
578 
        PASS_RC(ceata_init(8), 2, 1);
579 
        PASS_RC(ata_identify(ata_identify_data), 2, 2);
301 theseven 580 
    }
629 theseven 581 
    else
301 theseven 582 
    {
629 theseven 583 
        clockgate_enable(5, true);
584 
        ATA_CFG = BIT(0);
585 
        sleep(1000);
586 
        ATA_CFG = 0;
587 
        sleep(6000);
588 
        ATA_SWRST = BIT(0);
589 
        sleep(500);
590 
        ATA_SWRST = 0;
591 
        sleep(90000);
592 
        ATA_CONTROL = BIT(0);
593 
        sleep(200000);
594 
        ATA_PIO_TIME = 0x191f7;
595 
        ATA_PIO_LHR = 0;
596 
        while (!(ATA_PIO_READY & BIT(1))) sleep(100);
597 
        PASS_RC(ata_identify(ata_identify_data), 2, 0);
598 
        uint32_t piotime = 0x11f3;
599 
        uint32_t mdmatime = 0x1c175;
600 
        uint32_t udmatime = 0x5071152;
601 
        uint32_t param = 0;
602 
        ata_dma_flags = 0;
603 
        ata_lba48 = ata_identify_data[83] & BIT(10) ? true : false;
604 
        if (ata_identify_data[53] & BIT(1))
301 theseven 605 
        {
629 theseven 606 
            if (ata_identify_data[64] & BIT(1)) piotime = 0x2072;
607 
            else if (ata_identify_data[64] & BIT(0)) piotime = 0x7083;
301 theseven 608 
        }
629 theseven 609 
        if (ata_identify_data[63] & BIT(2))
301 theseven 610 
        {
629 theseven 611 
            mdmatime = 0x5072;
612 
            param = 0x22;
301 theseven 613 
        }
629 theseven 614 
        else if (ata_identify_data[63] & BIT(1))
301 theseven 615 
        {
629 theseven 616 
            mdmatime = 0x7083;
617 
            param = 0x21;
301 theseven 618 
        }
629 theseven 619 
        if (ata_identify_data[63] & BITRANGE(0, 2))
301 theseven 620 
        {
629 theseven 621 
            ata_dma_flags = BIT(3) | BIT(10);
622 
            param |= 0x20;
301 theseven 623 
        }
629 theseven 624 
        if (ata_identify_data[53] & BIT(2))
301 theseven 625 
        {
629 theseven 626 
            if (ata_identify_data[88] & BIT(4))
627 
            {
628 
                udmatime = 0x2010a52;
629 
                param = 0x44;
630 
            }
631 
            else if (ata_identify_data[88] & BIT(3))
632 
            {
633 
                udmatime = 0x2020a52;
634 
                param = 0x43;
635 
            }
636 
            else if (ata_identify_data[88] & BIT(2))
637 
            {
638 
                udmatime = 0x3030a52;
639 
                param = 0x42;
640 
            }
641 
            else if (ata_identify_data[88] & BIT(1))
642 
            {
643 
                udmatime = 0x3050a52;
644 
                param = 0x41;
645 
            }
646 
            if (ata_identify_data[88] & BITRANGE(0, 4))
647 
            {
648 
                ata_dma_flags = BIT(2) | BIT(3) | BIT(9) | BIT(10);
649 
                param |= 0x40;
650 
            }
301 theseven 651 
        }
629 theseven 652 
        ata_dma = param ? true : false;
653 
        PASS_RC(ata_set_feature(0xef, param), 2, 1);
654 
        if (ata_identify_data[82] & BIT(5)) PASS_RC(ata_set_feature(0x02, 0), 2, 2);
655 
        if (ata_identify_data[82] & BIT(6)) PASS_RC(ata_set_feature(0x55, 0), 2, 3);
656 
        ATA_PIO_TIME = piotime;
657 
        ATA_MDMA_TIME = mdmatime;
658 
        ATA_UDMA_TIME = udmatime;
301 theseven 659 
    }
629 theseven 660 
    if (ata_lba48)
661 
        ata_total_sectors = ata_identify_data[100]
662 
                            | (((uint64_t)ata_identify_data[101]) << 16)
663 
                            | (((uint64_t)ata_identify_data[102]) << 32)
664 
                            | (((uint64_t)ata_identify_data[103]) << 48);
665 
    else ata_total_sectors = ata_identify_data[60] | (((uint32_t)ata_identify_data[61]) << 16);
666 
    ata_total_sectors >>= 3;
301 theseven 667 
    ata_powered = true;
668 
    ata_set_active();
669 
    return 0;
670 
}
671 
 
672 
void ata_power_down()
673 
{
357 theseven 674 
    if (!ata_powered) return;
301 theseven 675 
    ata_powered = false;
629 theseven 676 
    if (ceata)
677 
    {
678 
        memset(ceata_taskfile, 0, 16);
679 
        ceata_taskfile[0xf] = 0xe0;
680 
        ceata_wait_idle();
681 
        ceata_write_multiple_register(0, ceata_taskfile, 16);
682 
        wakeup_wait(&mmc_comp_wakeup, CEATA_COMMAND_TIMEOUT);
683 
        sleep(30000);
684 
        clockgate_enable(9, false);
685 
    }
686 
    else
687 
    {
688 
        ata_wait_for_rdy(1000000);
689 
        ata_write_cbr(&ATA_PIO_DVR, 0);
690 
        ata_write_cbr(&ATA_PIO_CSD, 0xe0);
691 
        ata_wait_for_rdy(1000000);
692 
        sleep(30000);
693 
        ATA_CONTROL = 0;
694 
        while (!(ATA_CONTROL & BIT(1))) yield();
695 
        clockgate_enable(5, false);
696 
    }
301 theseven 697 
    i2c_sendbyte(0, 0xe6, 0x1b, 0);
698 
}
699 
 
337 theseven 700 
int ata_rw_chunk(uint64_t sector, uint32_t cnt, void* buffer, bool write)
701 
{
629 theseven 702 
    if (ceata)
337 theseven 703 
    {
629 theseven 704 
        memset(ceata_taskfile, 0, 16);
705 
        ceata_taskfile[0x2] = cnt >> 5;
706 
        ceata_taskfile[0x3] = sector >> 21;
707 
        ceata_taskfile[0x4] = sector >> 29;
708 
        ceata_taskfile[0x5] = sector >> 37;
709 
        ceata_taskfile[0xa] = cnt << 3;
710 
        ceata_taskfile[0xb] = sector << 3;
711 
        ceata_taskfile[0xc] = sector >> 5;
712 
        ceata_taskfile[0xd] = sector >> 13;
713 
        ceata_taskfile[0xf] = write ? 0x35 : 0x25;
714 
        PASS_RC(ceata_wait_idle(), 2, 0);
715 
        PASS_RC(ceata_write_multiple_register(0, ceata_taskfile, 16), 2, 1);
639 theseven 716 
        PASS_RC(ceata_rw_multiple_block(write, buffer, cnt << 3, CEATA_COMMAND_TIMEOUT), 2, 2);
337 theseven 717 
    }
718 
    else
719 
    {
629 theseven 720 
        PASS_RC(ata_wait_for_rdy(100000), 2, 0);
721 
        ata_write_cbr(&ATA_PIO_DVR, 0);
722 
        if (ata_lba48)
337 theseven 723 
        {
629 theseven 724 
            ata_write_cbr(&ATA_PIO_SCR, cnt >> 5);
725 
            ata_write_cbr(&ATA_PIO_SCR, (cnt << 3) & 0xff);
726 
            ata_write_cbr(&ATA_PIO_LHR, (sector >> 37) & 0xff);
727 
            ata_write_cbr(&ATA_PIO_LMR, (sector >> 29) & 0xff);
728 
            ata_write_cbr(&ATA_PIO_LLR, (sector >> 21) & 0xff);
729 
            ata_write_cbr(&ATA_PIO_LHR, (sector >> 13) & 0xff);
730 
            ata_write_cbr(&ATA_PIO_LMR, (sector >> 5) & 0xff);
731 
            ata_write_cbr(&ATA_PIO_LLR, (sector << 3) & 0xff);
732 
            ata_write_cbr(&ATA_PIO_DVR, BIT(6));
733 
            if (write) ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0x35 : 0x39);
734 
            else ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0x25 : 0x29);
337 theseven 735 
        }
736 
        else
737 
        {
629 theseven 738 
            ata_write_cbr(&ATA_PIO_SCR, (cnt << 3) & 0xff);
739 
            ata_write_cbr(&ATA_PIO_LHR, (sector >> 13) & 0xff);
740 
            ata_write_cbr(&ATA_PIO_LMR, (sector >> 5) & 0xff);
741 
            ata_write_cbr(&ATA_PIO_LLR, (sector << 3) & 0xff);
742 
            ata_write_cbr(&ATA_PIO_DVR, BIT(6) | ((sector >> 21) & 0xf));
743 
            if (write) ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0xca : 0x30);
744 
            else ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0xc8 : 0xc4);
337 theseven 745 
        }
629 theseven 746 
        if (ata_dma)
337 theseven 747 
        {
629 theseven 748 
            PASS_RC(ata_wait_for_start_of_transfer(500000), 2, 1);
749 
            if (write)
750 
            {
751 
                ATA_SBUF_START = buffer;
752 
                ATA_SBUF_SIZE = SECTOR_SIZE * cnt;
753 
                ATA_CFG |= BIT(4);
754 
            }
755 
            else
756 
            {
757 
                ATA_TBUF_START = buffer;
758 
                ATA_TBUF_SIZE = SECTOR_SIZE * cnt;
759 
                ATA_CFG &= ~BIT(4);
760 
            }
761 
            ATA_XFR_NUM = SECTOR_SIZE * cnt - 1;
762 
            ATA_CFG |= ata_dma_flags;
763 
            ATA_CFG &= ~(BIT(7) | BIT(8));
764 
            wakeup_wait(&ata_wakeup, TIMEOUT_NONE);
765 
            ATA_IRQ = BITRANGE(0, 4);
766 
            ATA_IRQ_MASK = BIT(0);
767 
            ATA_COMMAND = BIT(0);
768 
            if (wakeup_wait(&ata_wakeup, 500000) == THREAD_TIMEOUT)
769 
            {
770 
                ATA_COMMAND = BIT(1);
771 
                ATA_CFG &= ~(BITRANGE(2, 3) | BIT(12));
772 
                RET_ERR(2);
773 
            }
337 theseven 774 
            ATA_COMMAND = BIT(1);
775 
            ATA_CFG &= ~(BITRANGE(2, 3) | BIT(12));
776 
        }
629 theseven 777 
        else
337 theseven 778 
        {
629 theseven 779 
            cnt *= SECTOR_SIZE / 512;
780 
            while (cnt--)
781 
            {
782 
                int i;
783 
                PASS_RC(ata_wait_for_start_of_transfer(500000), 2, 1);
784 
                if (write)
785 
                    for (i = 0; i < 256; i++)
786 
                        ata_write_cbr(&ATA_PIO_DTR, ((uint16_t*)buffer)[i]);
787 
                else
788 
                    for (i = 0; i < 256; i++)
789 
                        ((uint16_t*)buffer)[i] = ata_read_cbr(&ATA_PIO_DTR);
790 
                buffer += 512;
791 
            }
337 theseven 792 
        }
629 theseven 793 
        PASS_RC(ata_wait_for_end_of_transfer(100000), 2, 3);
337 theseven 794 
    }
795 
    return 0;
796 
}
797 
 
613 theseven 798 
#ifdef ATA_HAVE_BBT
799 
int ata_bbt_translate(uint64_t sector, uint32_t count, uint64_t* phys, uint32_t* physcount)
800 
{
801 
    if (sector + count > ata_virtual_sectors) RET_ERR(0);
802 
    if (!ata_bbt)
803 
    {
804 
        *phys = sector;
805 
        *physcount = count;
806 
        return 0;
807 
    }
808 
    if (!count)
809 
    {
810 
        *phys = 0;
811 
        *physcount = 0;
812 
        return 0;
813 
    }
814 
    uint32_t offset;
815 
    uint32_t l0idx = sector >> 15;
816 
    uint32_t l0offs = sector & 0x7fff;
817 
    *physcount = MIN(count, 0x8000 - l0offs);
818 
    uint32_t l0data = ata_bbt[0][l0idx << 1];
819 
    uint32_t base = ata_bbt[0][(l0idx << 1) | 1] << 12;
820 
    if (l0data < 0x8000) offset = l0data + base;
821 
    else
822 
    {
823 
        uint32_t l1idx = (sector >> 10) & 0x1f;
824 
        uint32_t l1offs = sector & 0x3ff;
825 
        *physcount = MIN(count, 0x400 - l1offs);
826 
        uint32_t l1data = ata_bbt[l0data & 0x7fff][l1idx];
827 
        if (l1data < 0x8000) offset = l1data + base;
828 
        else
829 
        {
830 
            uint32_t l2idx = (sector >> 5) & 0x1f;
831 
            uint32_t l2offs = sector & 0x1f;
832 
            *physcount = MIN(count, 0x20 - l2offs);
833 
            uint32_t l2data = ata_bbt[l1data & 0x7fff][l2idx];
834 
            if (l2data < 0x8000) offset = l2data + base;
835 
            else
836 
            {
837 
                uint32_t l3idx = sector & 0x1f;
838 
                uint32_t l3data = ata_bbt[l2data & 0x7fff][l3idx];
839 
                for (*physcount = 1; *physcount < count && l3idx + *physcount < 0x20; *physcount++)
840 
                    if (ata_bbt[l2data & 0x7fff][l3idx + *physcount] != l3data)
841 
                        break;
842 
                offset = l3data + base;
843 
            }
844 
        }
845 
    }
846 
    *phys = sector + offset;
847 
    return 0;
848 
}
849 
#endif
850 
 
301 theseven 851 
int ata_rw_sectors(uint64_t sector, uint32_t count, void* buffer, bool write)
852 
{
627 theseven 853 
    if (((uint32_t)buffer) & (CACHEALIGN_SIZE - 1))
854 
        panicf(PANIC_KILLTHREAD,
855 
               "ATA: Misaligned data buffer at %08X (sector %lu, count %lu)",
856 
               (unsigned int)buffer, (unsigned int)sector, count);
328 theseven 857 
#ifdef ATA_HAVE_BBT
858 
    if (sector + count > ata_virtual_sectors) RET_ERR(0);
430 theseven 859 
    if (ata_bbt)
860 
        while (count)
328 theseven 861 
        {
613 theseven 862 
            uint64_t phys;
863 
            uint32_t cnt;
864 
            PASS_RC(ata_bbt_translate(sector, count, &phys, &cnt), 0, 0);
865 
            uint32_t offset = phys - sector;
430 theseven 866 
            if (offset != ata_last_offset && phys - ata_last_phys < 64) ata_soft_reset();
867 
            ata_last_offset = offset;
868 
            ata_last_phys = phys + cnt;
869 
            PASS_RC(ata_rw_sectors_internal(phys, cnt, buffer, write), 0, 0);
870 
            buffer += cnt * SECTOR_SIZE;
871 
            sector += cnt;
872 
            count -= cnt;
328 theseven 873 
        }
430 theseven 874 
    else PASS_RC(ata_rw_sectors_internal(sector, count, buffer, write), 0, 0);
328 theseven 875 
    return 0;
876 
}
877 
 
878 
int ata_rw_sectors_internal(uint64_t sector, uint32_t count, void* buffer, bool write)
879 
{
880 
#endif
301 theseven 881 
    if (sector + count > ata_total_sectors) RET_ERR(0);
882 
    if (!ata_powered) ata_power_up();
883 
    ata_set_active();
884 
    if (ata_dma && write) clean_dcache();
885 
    else if (ata_dma) invalidate_dcache();
629 theseven 886 
    if (!ceata) ATA_COMMAND = BIT(1);
301 theseven 887 
    while (count)
888 
    {
317 theseven 889 
        uint32_t cnt = MIN(ata_lba48 ? 8192 : 32, count);
337 theseven 890 
        int rc = -1;
613 theseven 891 
        rc = ata_rw_chunk(sector, cnt, buffer, write);
620 theseven 892 
        if (rc && ata_error_srst) ata_soft_reset();
893 
        if (rc && ata_retries)
301 theseven 894 
        {
337 theseven 895 
            void* buf = buffer;
405 theseven 896 
            uint64_t sect;
337 theseven 897 
            for (sect = sector; sect < sector + cnt; sect++)
898 
            {
899 
                rc = -1;
620 theseven 900 
                int tries = ata_retries;
337 theseven 901 
                while (tries-- && rc)
902 
                {
903 
                    rc = ata_rw_chunk(sect, 1, buf, write);
620 theseven 904 
                    if (rc && ata_error_srst) ata_soft_reset();
337 theseven 905 
                }
906 
                if (rc) break;
907 
                buf += SECTOR_SIZE;
908 
            }
301 theseven 909 
        }
337 theseven 910 
        PASS_RC(rc, 1, 1);
911 
        buffer += SECTOR_SIZE * cnt;
301 theseven 912 
        sector += cnt;
913 
        count -= cnt;
914 
    }
915 
    ata_set_active();
916 
    return 0;
917 
}
918 
 
919 
static void ata_thread(void)
920 
{
921 
    while (true)
922 
    {
923 
        mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
924 
        if (TIME_AFTER(USEC_TIMER, ata_last_activity_value + ata_sleep_timeout) && ata_powered)
925 
            ata_power_down();
926 
        mutex_unlock(&ata_mutex);
927 
        sleep(1000000);
928 
    }
929 
}
930 
 
931 
/* API Functions */
932 
int ata_soft_reset()
933 
{
629 theseven 934 
    int rc;
301 theseven 935 
    mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
936 
    if (!ata_powered) ata_power_up();
937 
    ata_set_active();
629 theseven 938 
    if (ceata) rc = ceata_soft_reset();
939 
    else
940 
    {
941 
        ata_write_cbr(&ATA_PIO_DAD, BIT(1) | BIT(2));
942 
        sleep(10);
943 
        ata_write_cbr(&ATA_PIO_DAD, 0);
944 
        rc = ata_wait_for_rdy(20000000);
945 
    }
613 theseven 946 
    if (IS_ERR(rc))
947 
    {
948 
        ata_power_down();
949 
        sleep(3000000);
950 
        ata_power_up();
951 
    }
301 theseven 952 
    ata_set_active();
953 
    mutex_unlock(&ata_mutex);
620 theseven 954 
    return rc;
301 theseven 955 
}
956 
 
957 
int ata_read_sectors(IF_MD2(int drive,) unsigned long start, int incount,
958 
                     void* inbuf)
959 
{
960 
    mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
337 theseven 961 
    int rc = ata_rw_sectors(start, incount, inbuf, false);
301 theseven 962 
    mutex_unlock(&ata_mutex);
963 
    return rc;
964 
}
965 
 
966 
int ata_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
967 
                      const void* outbuf)
968 
{
969 
    mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
337 theseven 970 
    int rc = ata_rw_sectors(start, count, (void*)((uint32_t)outbuf), true);
301 theseven 971 
    mutex_unlock(&ata_mutex);
972 
    return rc;
973 
}
974 
 
337 theseven 975 
void ata_spindown(int seconds)
976 
{
977 
    ata_sleep_timeout = seconds * 1000000;
978 
}
301 theseven 979 
 
980 
void ata_sleep(void)
981 
{
982 
    mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
983 
    ata_power_down();
984 
    mutex_unlock(&ata_mutex);
985 
}
986 
 
987 
void ata_sleepnow(void)
988 
{
989 
    ata_sleep();
990 
}
991 
 
992 
void ata_close(void)
993 
{
994 
    ata_sleep();
995 
}
996 
 
997 
void ata_spin(void)
998 
{
999 
    ata_power_up();
1000 
}
1001 
 
1002 
void ata_get_info(IF_MD2(int drive,) struct storage_info *info)
1003 
{
1004 
    (*info).sector_size = SECTOR_SIZE;
328 theseven 1005 
#ifdef ATA_HAVE_BBT
1006 
    (*info).num_sectors = ata_virtual_sectors;
1007 
#else
301 theseven 1008 
    (*info).num_sectors = ata_total_sectors;
328 theseven 1009 
#endif
301 theseven 1010 
    (*info).vendor = "Apple";
1011 
    (*info).product = "iPod Classic";
1012 
    (*info).revision = "1.0";
613 theseven 1013 
    (*info).driverinfo = &drvinfo;
301 theseven 1014 
}
1015 
 
1016 
long ata_last_disk_activity(void)
1017 
{
1018 
    return ata_last_activity_value;
1019 
}
1020 
 
613 theseven 1021 
#ifdef ATA_HAVE_BBT
1022 
void ata_bbt_disable()
301 theseven 1023 
{
328 theseven 1024 
    mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
613 theseven 1025 
    if (ata_bbt) free(ata_bbt);
430 theseven 1026 
    ata_bbt = NULL;
613 theseven 1027 
    ata_virtual_sectors = ata_total_sectors;
1028 
    mutex_unlock(&ata_mutex);
1029 
}
1030 
 
1031 
void ata_bbt_reload()
1032 
{
1033 
    mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
1034 
    ata_bbt_disable();
328 theseven 1035 
    ata_power_up();
430 theseven 1036 
    uint32_t* buf = (uint32_t*)memalign(0x10, 0x1000);
1037 
    if (buf)
328 theseven 1038 
    {
620 theseven 1039 
        if (IS_ERR(ata_bbt_read_sectors(0, 1, buf)))
1040 
            ata_virtual_sectors = ata_total_sectors;
1041 
        else if (!memcmp(buf, "emBIbbth", 8))
328 theseven 1042 
        {
430 theseven 1043 
            ata_virtual_sectors = (((uint64_t)buf[0x1fd]) << 32) | buf[0x1fc];
1044 
            uint32_t count = buf[0x1ff];
1045 
            ata_bbt = (typeof(ata_bbt))memalign(0x10, 0x1000 * count);
620 theseven 1046 
            if (!ata_bbt)
430 theseven 1047 
            {
620 theseven 1048 
                cprintf(CONSOLE_BOOT, "ATA: Failed to allocate memory for BBT! (%d bytes)",
1049 
                        0x1000 * count);
1050 
                ata_virtual_sectors = ata_total_sectors;
1051 
            }
1052 
            else
1053 
            {
1054 
                uint32_t i;
1055 
                uint32_t cnt;
1056 
                for (i = 0; i < count; i += cnt)
1057 
                {
1058 
                    uint32_t phys = buf[0x200 + i];
1059 
                    for (cnt = 1; cnt < count; cnt++)
1060 
                        if (buf[0x200 + i + cnt] != phys + cnt)
1061 
                            break;
1062 
                    if (IS_ERR(ata_bbt_read_sectors(phys, cnt, ata_bbt[i << 6])))
1063 
                    {
1064 
                        free(ata_bbt);
1065 
                        ata_virtual_sectors = ata_total_sectors;
430 theseven 1066 
                        break;
620 theseven 1067 
                    }
1068 
                }
1069 
                if (ata_bbt) reownalloc(ata_bbt, NULL);
430 theseven 1070 
            }
328 theseven 1071 
        }
430 theseven 1072 
        else ata_virtual_sectors = ata_total_sectors;
1073 
        free(buf);
328 theseven 1074 
    }
437 theseven 1075 
    else ata_virtual_sectors = ata_total_sectors;
328 theseven 1076 
    mutex_unlock(&ata_mutex);
613 theseven 1077 
}
328 theseven 1078 
#endif
613 theseven 1079 
 
1080 
int ata_init(void)
1081 
{
1082 
    mutex_init(&ata_mutex);
1083 
    wakeup_init(&ata_wakeup);
629 theseven 1084 
    wakeup_init(&mmc_wakeup);
1085 
    wakeup_init(&mmc_comp_wakeup);
1086 
    ceata = PDAT(11) & BIT(1);
1087 
    if (ceata)
1088 
    {
1089 
        ata_lba48 = true;
1090 
        ata_dma = true;
1091 
        PCON(8) = 0x33333333;
1092 
        PCON(9) = (PCON(9) & ~0xff) | 0x33;
1093 
        PCON(11) |= 0xf;
1094 
        *((uint32_t volatile*)0x38a00000) = 0;
1095 
        *((uint32_t volatile*)0x38700000) = 0;
1096 
    }
1097 
    else
1098 
    {
1099 
        PCON(7) = 0x44444444;
1100 
        PCON(8) = 0x44444444;
1101 
        PCON(9) = 0x44444444;
1102 
        PCON(10) = (PCON(10) & ~0xffff) | 0x4444;
1103 
    }
613 theseven 1104 
    ata_powered = false;
1105 
    ata_total_sectors = 0;
1106 
#ifdef ATA_HAVE_BBT
1107 
    ata_bbt_reload();
1108 
#endif
429 theseven 1109 
    thread_create(&ata_thread_handle, "ATA idle monitor", ata_thread, ata_stack,
543 theseven 1110 
                  sizeof(ata_stack), OS_THREAD, 1, true);
301 theseven 1111 
    return 0;
1112 
}
1113 
 
1114 
int ata_num_drives(int first_drive)
1115 
{
1116 
    /* We don't care which logical drive number(s) we have been assigned */
1117 
    (void)first_drive;
1118 
 
1119 
    return 1;
1120 
}
1121 
 
1122 
void INT_ATA()
1123 
{
1124 
    uint32_t ata_irq = ATA_IRQ;
1125 
    ATA_IRQ = ata_irq;
1126 
    if (ata_irq & ATA_IRQ_MASK) wakeup_signal(&ata_wakeup);
1127 
    ATA_IRQ_MASK = 0;
1128 
}
629 theseven 1129 
 
1130 
void INT_MMC()
1131 
{
1132 
    uint32_t irq = SDCI_IRQ;
1133 
    if (irq & SDCI_IRQ_DAT_DONE_INT) wakeup_signal(&mmc_wakeup);
1134 
    if (irq & SDCI_IRQ_IOCARD_IRQ_INT) wakeup_signal(&mmc_comp_wakeup);
1135 
    SDCI_IRQ = irq;
1136 
}