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301 theseven 1 
/***************************************************************************
2 
 *             __________               __   ___.
3 
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
4 
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
5 
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
6 
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
7 
 *                     \/            \/     \/    \/            \/
8 
 * $Id$
9 
 *
10 
 * Copyright (C) 2007 Dave Chapman
11 
 *
12 
 * This program is free software; you can redistribute it and/or
13 
 * modify it under the terms of the GNU General Public License
14 
 * as published by the Free Software Foundation; either version 2
15 
 * of the License, or (at your option) any later version.
16 
 *
17 
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 
 * KIND, either express or implied.
19 
 *
20 
 ****************************************************************************/
21 
#include "global.h"
22 
#include "thread.h"
23 
#include "disk.h"
24 
#include "storage.h"
339 theseven 25 
#include "storage_ata-target.h"
301 theseven 26 
#include "timer.h"
629 theseven 27 
#include "constants/mmc.h"
301 theseven 28 
#include "../ipodnano3g/s5l8702.h"
29 
 
613 theseven 30 
 
31 
#ifndef ATA_RETRIES
32 
#define ATA_RETRIES 3
33 
#endif
34 
 
35 
 
629 theseven 36 
#define CEATA_POWERUP_TIMEOUT 30000000
37 
#define CEATA_COMMAND_TIMEOUT 1000000
38 
#define CEATA_DAT_NONBUSY_TIMEOUT 5000000
39 
#define CEATA_MMC_RCA 1
40 
 
41 
 
301 theseven 42 
/** static, private data **/
629 theseven 43 
static uint8_t ceata_taskfile[16] __attribute__((aligned(16)));
636 theseven 44 
uint16_t ata_identify_data[0x100] __attribute__((aligned(16)));
629 theseven 45 
bool ceata;
301 theseven 46 
bool ata_lba48;
47 
bool ata_dma;
48 
uint64_t ata_total_sectors;
601 theseven 49 
struct mutex ata_mutex;
301 theseven 50 
static struct wakeup ata_wakeup;
51 
static uint32_t ata_dma_flags;
52 
static long ata_last_activity_value = -1;
53 
static long ata_sleep_timeout = 20000000;
429 theseven 54 
static struct scheduler_thread ata_thread_handle;
55 
static uint32_t ata_stack[0x80] STACK_ATTR;
301 theseven 56 
static bool ata_powered;
620 theseven 57 
static int ata_retries = ATA_RETRIES;
58 
static bool ata_error_srst = true;
629 theseven 59 
static struct wakeup mmc_wakeup;
60 
static struct wakeup mmc_comp_wakeup;
301 theseven 61 
 
629 theseven 62 
 
328 theseven 63 
#ifdef ATA_HAVE_BBT
64 
#include "panic.h"
430 theseven 65 
uint16_t (*ata_bbt)[0x20];
339 theseven 66 
uint64_t ata_virtual_sectors;
337 theseven 67 
uint32_t ata_last_offset;
68 
uint64_t ata_last_phys;
301 theseven 69 
 
620 theseven 70 
int ata_bbt_read_sectors(uint32_t sector, uint32_t count, void* buffer)
328 theseven 71 
{
620 theseven 72 
    if (ata_last_phys != sector - 1 && ata_last_phys > sector - 64) ata_soft_reset();
328 theseven 73 
    int rc = ata_rw_sectors_internal(sector, count, buffer, false);
620 theseven 74 
    if (rc) rc = ata_rw_sectors_internal(sector, count, buffer, false);
75 
    ata_last_phys = sector + count - 1;
76 
    ata_last_offset = 0;
328 theseven 77 
    if (IS_ERR(rc))
620 theseven 78 
        cprintf(CONSOLE_BOOT, "ATA: Error %08X while reading BBT (sector %d, count %d)\n",
79 
                rc, sector, count);
80 
    return rc;
328 theseven 81 
}
82 
#endif
83 
 
613 theseven 84 
static struct ata_target_driverinfo drvinfo =
85 
{
620 theseven 86 
    .set_retries = ata_set_retries,
87 
    .srst_after_error = ata_srst_after_error,
613 theseven 88 
#ifdef ATA_HAVE_BBT
89 
    .bbt_translate = ata_bbt_translate,
90 
    .bbt_reload = ata_bbt_reload,
91 
    .bbt_disable = ata_bbt_disable
92 
#endif
93 
};
328 theseven 94 
 
613 theseven 95 
 
620 theseven 96 
void ata_set_retries(int retries)
97 
{
98 
    ata_retries = retries;
99 
}
100 
 
101 
void ata_srst_after_error(bool enable)
102 
{
103 
    ata_error_srst = enable;
104 
}
105 
 
301 theseven 106 
static uint16_t ata_read_cbr(uint32_t volatile* reg)
107 
{
317 theseven 108 
    while (!(ATA_PIO_READY & 2)) yield();
301 theseven 109 
    volatile uint32_t dummy = *reg;
317 theseven 110 
    while (!(ATA_PIO_READY & 1)) yield();
301 theseven 111 
    return ATA_PIO_RDATA;
112 
}
113 
 
114 
static void ata_write_cbr(uint32_t volatile* reg, uint16_t data)
115 
{
317 theseven 116 
    while (!(ATA_PIO_READY & 2)) yield();
301 theseven 117 
    *reg = data;
118 
}
119 
 
120 
static int ata_wait_for_not_bsy(long timeout)
121 
{
122 
    long startusec = USEC_TIMER;
123 
    while (true)
124 
    {
125 
        uint8_t csd = ata_read_cbr(&ATA_PIO_CSD);
126 
        if (!(csd & BIT(7))) return 0;
127 
        if (TIMEOUT_EXPIRED(startusec, timeout)) RET_ERR(0);
128 
    }
129 
}
130 
 
131 
static int ata_wait_for_rdy(long timeout)
132 
{
133 
    long startusec = USEC_TIMER;
134 
    PASS_RC(ata_wait_for_not_bsy(timeout), 1, 0);
135 
    while (true)
136 
    {
137 
        uint8_t dad = ata_read_cbr(&ATA_PIO_DAD);
138 
        if (dad & BIT(6)) return 0;
139 
        if (TIMEOUT_EXPIRED(startusec, timeout)) RET_ERR(1);
140 
    }
141 
}
142 
 
143 
static int ata_wait_for_start_of_transfer(long timeout)
144 
{
145 
    long startusec = USEC_TIMER;
146 
    PASS_RC(ata_wait_for_not_bsy(timeout), 2, 0);
147 
    while (true)
148 
    {
149 
        uint8_t dad = ata_read_cbr(&ATA_PIO_DAD);
150 
        if (dad & BIT(0)) RET_ERR(1);
151 
        if ((dad & (BIT(7) | BIT(3))) == BIT(3)) return 0;
152 
        if (TIMEOUT_EXPIRED(startusec, timeout)) RET_ERR(2);
153 
    }
154 
}
155 
 
156 
static int ata_wait_for_end_of_transfer(long timeout)
157 
{
158 
    PASS_RC(ata_wait_for_not_bsy(timeout), 2, 0);
159 
    uint8_t dad = ata_read_cbr(&ATA_PIO_DAD);
160 
    if (dad & BIT(0)) RET_ERR(1);
161 
    if ((dad & (BIT(3) | BITRANGE(5, 7))) == BIT(6)) return 0;
162 
    RET_ERR(2);
163 
}
164 
 
629 theseven 165 
int mmc_dsta_check_command_success(bool disable_crc)
166 
{
167 
    int rc = 0;
168 
    uint32_t dsta = SDCI_DSTA;
169 
    if (dsta & SDCI_DSTA_RESTOUTE) rc |= 1;
170 
    if (dsta & SDCI_DSTA_RESENDE) rc |= 2;
171 
    if (dsta & SDCI_DSTA_RESINDE) rc |= 4;
172 
    if (!disable_crc)
173 
        if (dsta & SDCI_DSTA_RESCRCE)
174 
            rc |= 8;
175 
    if (rc) RET_ERR(rc);
176 
    return 0;
177 
}
178 
 
179 
bool mmc_send_command(uint32_t cmd, uint32_t arg, uint32_t* result, int timeout)
180 
{
181 
    long starttime = USEC_TIMER;
182 
    while ((SDCI_STATE & SDCI_STATE_CMD_STATE_MASK) != SDCI_STATE_CMD_STATE_CMD_IDLE)
183 
    {
184 
        if (TIMEOUT_EXPIRED(starttime, timeout)) RET_ERR(0);
185 
        yield();
186 
    }
187 
    SDCI_STAC = SDCI_STAC_CLR_CMDEND | SDCI_STAC_CLR_BIT_3
188 
              | SDCI_STAC_CLR_RESEND | SDCI_STAC_CLR_DATEND
189 
              | SDCI_STAC_CLR_DAT_CRCEND | SDCI_STAC_CLR_CRC_STAEND
190 
              | SDCI_STAC_CLR_RESTOUTE | SDCI_STAC_CLR_RESENDE
191 
              | SDCI_STAC_CLR_RESINDE | SDCI_STAC_CLR_RESCRCE
192 
              | SDCI_STAC_CLR_WR_DATCRCE | SDCI_STAC_CLR_RD_DATCRCE
193 
              | SDCI_STAC_CLR_RD_DATENDE0 | SDCI_STAC_CLR_RD_DATENDE1
194 
              | SDCI_STAC_CLR_RD_DATENDE2 | SDCI_STAC_CLR_RD_DATENDE3
195 
              | SDCI_STAC_CLR_RD_DATENDE4 | SDCI_STAC_CLR_RD_DATENDE5
196 
              | SDCI_STAC_CLR_RD_DATENDE6 | SDCI_STAC_CLR_RD_DATENDE7;
197 
    SDCI_ARGU = arg;
198 
    SDCI_CMD = cmd;
199 
    if (!(SDCI_DSTA & SDCI_DSTA_CMDRDY)) RET_ERR(1);
200 
    SDCI_CMD = cmd | SDCI_CMD_CMDSTR;
201 
    sleep(1000);
202 
    while (!(SDCI_DSTA & SDCI_DSTA_CMDEND))
203 
    {
204 
        if (TIMEOUT_EXPIRED(starttime, timeout)) RET_ERR(2);
205 
        yield();
206 
    }
207 
    if ((cmd & SDCI_CMD_RES_TYPE_MASK) != SDCI_CMD_RES_TYPE_NONE)
208 
    {
209 
        while (!(SDCI_DSTA & SDCI_DSTA_RESEND))
210 
        {
211 
            if (TIMEOUT_EXPIRED(starttime, timeout)) RET_ERR(3);
212 
            yield();
213 
        }
214 
        if (cmd & SDCI_CMD_RES_BUSY)
215 
            while (SDCI_DSTA & SDCI_DSTA_DAT_BUSY)
216 
            {
217 
                if (TIMEOUT_EXPIRED(starttime, CEATA_DAT_NONBUSY_TIMEOUT)) RET_ERR(4);
218 
                yield();
219 
            }
220 
    }
221 
    bool nocrc = (cmd & SDCI_CMD_RES_SIZE_MASK) == SDCI_CMD_RES_SIZE_136;
222 
    PASS_RC(mmc_dsta_check_command_success(nocrc), 3, 5);
223 
    if (result) *result = SDCI_RESP0;
224 
    return 0;
225 
}
226 
 
227 
int mmc_get_card_status(uint32_t* result)
228 
{
229 
    return mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SEND_STATUS)
230 
                          | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
231 
                          | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
232 
                            MMC_CMD_SEND_STATUS_RCA(CEATA_MMC_RCA), result, CEATA_COMMAND_TIMEOUT);
233 
}
234 
 
235 
int mmc_init()
236 
{
237 
    sleep(100000);
238 
    PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_GO_IDLE_STATE)
239 
                           | SDCI_CMD_CMD_TYPE_BC | SDCI_CMD_RES_TYPE_NONE
240 
                           | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NID,
241 
                             0, NULL, CEATA_COMMAND_TIMEOUT), 3, 0);
242 
    long startusec = USEC_TIMER;
243 
    uint32_t result;
244 
    do
245 
    {
246 
        if (TIMEOUT_EXPIRED(startusec, CEATA_POWERUP_TIMEOUT)) RET_ERR(1);
247 
        sleep(1000);
248 
        PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SEND_OP_COND)
249 
                               | SDCI_CMD_CMD_TYPE_BCR | SDCI_CMD_RES_TYPE_R3
250 
                               | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NID,
251 
                                 MMC_CMD_SEND_OP_COND_OCR(MMC_OCR_270_360),
252 
                                 NULL, CEATA_COMMAND_TIMEOUT), 3, 2);
253 
        result = SDCI_RESP0;
254 
    }
255 
    while (!(result & MMC_OCR_POWER_UP_DONE));
256 
    PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_ALL_SEND_CID)
257 
                           | SDCI_CMD_CMD_TYPE_BCR | SDCI_CMD_RES_TYPE_R2
258 
                           | SDCI_CMD_RES_SIZE_136 | SDCI_CMD_NCR_NID_NID,
259 
                             0, NULL, CEATA_COMMAND_TIMEOUT), 3, 3);
260 
    PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SET_RELATIVE_ADDR)
261 
                           | SDCI_CMD_CMD_TYPE_BCR | SDCI_CMD_RES_TYPE_R1
262 
                           | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
263 
                             MMC_CMD_SET_RELATIVE_ADDR_RCA(CEATA_MMC_RCA),
264 
                             NULL, CEATA_COMMAND_TIMEOUT), 3, 4);
265 
    PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SELECT_CARD)
266 
                           | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
267 
                           | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
268 
                             MMC_CMD_SELECT_CARD_RCA(CEATA_MMC_RCA),
269 
                             NULL, CEATA_COMMAND_TIMEOUT), 3, 5);
270 
    PASS_RC(mmc_get_card_status(&result), 3, 6);
271 
    if ((result & MMC_STATUS_CURRENT_STATE_MASK) != MMC_STATUS_CURRENT_STATE_TRAN) RET_ERR(7);
272 
    return 0;
273 
}
274 
 
275 
int mmc_fastio_write(uint32_t addr, uint32_t data)
276 
{
277 
    return mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_FAST_IO)
278 
                          | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R4
279 
                          | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
280 
                            MMC_CMD_FAST_IO_RCA(CEATA_MMC_RCA) | MMC_CMD_FAST_IO_DIRECTION_WRITE
281 
                          | MMC_CMD_FAST_IO_ADDRESS(addr) | MMC_CMD_FAST_IO_DATA(data),
282 
                            NULL, CEATA_COMMAND_TIMEOUT);
283 
}
284 
 
285 
int mmc_fastio_read(uint32_t addr, uint32_t* data)
286 
{
287 
    return mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_FAST_IO)
288 
                          | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R4
289 
                          | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
290 
                            MMC_CMD_FAST_IO_RCA(CEATA_MMC_RCA) | MMC_CMD_FAST_IO_DIRECTION_READ
291 
                          | MMC_CMD_FAST_IO_ADDRESS(addr), data, CEATA_COMMAND_TIMEOUT);
292 
}
293 
 
294 
int ceata_soft_reset()
295 
{
296 
    PASS_RC(mmc_fastio_write(6, 4), 2, 0);
297 
    sleep(1000);
298 
    PASS_RC(mmc_fastio_write(6, 0), 2, 1);
299 
    sleep(10000);
300 
    long startusec = USEC_TIMER;
301 
    uint32_t status;
302 
    do
303 
    {
304 
        PASS_RC(mmc_fastio_read(0xf, &status), 2, 2);
305 
        if (TIMEOUT_EXPIRED(startusec, CEATA_POWERUP_TIMEOUT)) RET_ERR(3);
306 
        sleep(1000);
307 
    }
308 
    while (status & 0x80);
309 
    return 0;
310 
}
311 
 
312 
int mmc_dsta_check_data_success()
313 
{
314 
    int rc = 0;
315 
    uint32_t dsta = SDCI_DSTA;
316 
    if (dsta & (SDCI_DSTA_WR_DATCRCE | SDCI_DSTA_RD_DATCRCE))
317 
    {
318 
        if (dsta & SDCI_DSTA_WR_DATCRCE) rc |= 1;
319 
        if (dsta & SDCI_DSTA_RD_DATCRCE) rc |= 2;
320 
        if ((dsta & SDCI_DSTA_WR_CRC_STATUS_MASK) == SDCI_DSTA_WR_CRC_STATUS_TXERR) rc |= 4;
321 
        else if ((dsta & SDCI_DSTA_WR_CRC_STATUS_MASK) == SDCI_DSTA_WR_CRC_STATUS_CARDERR) rc |= 8;
322 
    }
323 
    if (dsta & (SDCI_DSTA_RD_DATENDE0 | SDCI_DSTA_RD_DATENDE1 | SDCI_DSTA_RD_DATENDE2
324 
              | SDCI_DSTA_RD_DATENDE3 | SDCI_DSTA_RD_DATENDE4 | SDCI_DSTA_RD_DATENDE5
325 
              | SDCI_DSTA_RD_DATENDE6 | SDCI_DSTA_RD_DATENDE7))
326 
        rc |= 16;
327 
    if (rc) RET_ERR(rc);
328 
    return 0;
329 
}
330 
 
331 
void mmc_discard_irq()
332 
{
333 
    SDCI_IRQ = SDCI_IRQ_DAT_DONE_INT | SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT
334 
             | SDCI_IRQ_MASK_MASK_READ_WAIT_INT;
335 
    wakeup_wait(&mmc_wakeup, TIMEOUT_NONE);
336 
}
337 
 
338 
int ceata_read_multiple_register(uint32_t addr, void* dest, uint32_t size)
339 
{
340 
    if (size > 0x10) RET_ERR(0);
341 
    mmc_discard_irq();
342 
    SDCI_DMASIZE = size;
343 
    SDCI_DMACOUNT = 1;
344 
    SDCI_DMAADDR = dest;
345 
    SDCI_DCTRL = SDCI_DCTRL_TXFIFORST | SDCI_DCTRL_RXFIFORST;
636 theseven 346 
    invalidate_dcache();
629 theseven 347 
    PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_REG)
348 
                           | SDCI_CMD_CMD_TYPE_ADTC | SDCI_CMD_RES_TYPE_R1
349 
                           | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
350 
                             MMC_CMD_CEATA_RW_MULTIPLE_REG_DIRECTION_READ
351 
                           | MMC_CMD_CEATA_RW_MULTIPLE_REG_ADDRESS(addr & 0xfc)
352 
                           | MMC_CMD_CEATA_RW_MULTIPLE_REG_COUNT(size & 0xfc),
353 
                             NULL, CEATA_COMMAND_TIMEOUT), 2, 1);
354 
    long startusec = USEC_TIMER;
355 
    if (wakeup_wait(&mmc_wakeup, CEATA_COMMAND_TIMEOUT) == THREAD_TIMEOUT) RET_ERR(2);
356 
    PASS_RC(mmc_dsta_check_data_success(), 2, 3);
357 
    return 0;
358 
}
359 
 
360 
int ceata_write_multiple_register(uint32_t addr, void* dest, uint32_t size)
361 
{
362 
    int i;
363 
    if (size > 0x10) RET_ERR(0);
364 
    mmc_discard_irq();
365 
    SDCI_DMASIZE = size;
366 
    SDCI_DMACOUNT = 0;
367 
    SDCI_DCTRL = SDCI_DCTRL_TXFIFORST | SDCI_DCTRL_RXFIFORST;
368 
    PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_REG)
369 
                           | SDCI_CMD_CMD_TYPE_ADTC | SDCI_CMD_CMD_RD_WR
370 
                           | SDCI_CMD_RES_BUSY | SDCI_CMD_RES_TYPE_R1
371 
                           | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
372 
                             MMC_CMD_CEATA_RW_MULTIPLE_REG_DIRECTION_WRITE
373 
                           | MMC_CMD_CEATA_RW_MULTIPLE_REG_ADDRESS(addr & 0xfc)
374 
                           | MMC_CMD_CEATA_RW_MULTIPLE_REG_COUNT(size & 0xfc),
375 
                             NULL, CEATA_COMMAND_TIMEOUT), 3, 1);
376 
    SDCI_DCTRL = SDCI_DCTRL_TRCONT_TX;
377 
    for (i = 0; i < size / 4; i++) SDCI_DATA = ((uint32_t*)dest)[i];
378 
    long startusec = USEC_TIMER;
379 
    if (wakeup_wait(&mmc_wakeup, CEATA_COMMAND_TIMEOUT) == THREAD_TIMEOUT) RET_ERR(2);
380 
    while ((SDCI_STATE & SDCI_STATE_DAT_STATE_MASK) != SDCI_STATE_DAT_STATE_IDLE)
381 
    {
382 
        if (TIMEOUT_EXPIRED(startusec, CEATA_COMMAND_TIMEOUT)) RET_ERR(3);
383 
        yield();
384 
    }
385 
    PASS_RC(mmc_dsta_check_data_success(), 3, 4);
386 
    return 0;
387 
}
388 
 
389 
int ceata_init(int buswidth)
390 
{
391 
    uint32_t result;
392 
    PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SWITCH) | SDCI_CMD_RES_BUSY
393 
                           | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
394 
                           | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
395 
                             MMC_CMD_SWITCH_ACCESS_WRITE_BYTE
396 
                           | MMC_CMD_SWITCH_INDEX(MMC_CMD_SWITCH_FIELD_HS_TIMING)
397 
                           | MMC_CMD_SWITCH_VALUE(MMC_CMD_SWITCH_FIELD_HS_TIMING_HIGH_SPEED),
398 
                             &result, CEATA_COMMAND_TIMEOUT), 3, 0);
399 
    if (result & MMC_STATUS_SWITCH_ERROR) RET_ERR(1);
400 
    if (buswidth > 1)
401 
    {
402 
        int setting;
403 
        if (buswidth == 4) setting = MMC_CMD_SWITCH_FIELD_BUS_WIDTH_4BIT;
404 
        else if (buswidth == 8) setting = MMC_CMD_SWITCH_FIELD_BUS_WIDTH_8BIT;
405 
        else setting = MMC_CMD_SWITCH_FIELD_BUS_WIDTH_1BIT;
406 
        PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SWITCH) | SDCI_CMD_RES_BUSY
407 
                               | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
408 
                               | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
409 
                                 MMC_CMD_SWITCH_ACCESS_WRITE_BYTE
410 
                               | MMC_CMD_SWITCH_INDEX(MMC_CMD_SWITCH_FIELD_BUS_WIDTH)
411 
                               | MMC_CMD_SWITCH_VALUE(setting),
412 
                                 &result, CEATA_COMMAND_TIMEOUT), 3, 2);
413 
        if (result & MMC_STATUS_SWITCH_ERROR) RET_ERR(3);
414 
        if (buswidth == 4)
415 
            SDCI_CTRL = (SDCI_CTRL & ~SDCI_CTRL_BUS_WIDTH_MASK) | SDCI_CTRL_BUS_WIDTH_4BIT;
416 
        else if (buswidth == 8)
417 
            SDCI_CTRL = (SDCI_CTRL & ~SDCI_CTRL_BUS_WIDTH_MASK) | SDCI_CTRL_BUS_WIDTH_8BIT;
418 
    }
419 
    PASS_RC(ceata_soft_reset(), 3, 4);
420 
    PASS_RC(ceata_read_multiple_register(0, ceata_taskfile, 0x10), 3, 5);
421 
    if (ceata_taskfile[0xc] != 0xce || ceata_taskfile[0xd] != 0xaa) RET_ERR(6);
422 
    PASS_RC(mmc_fastio_write(6, 0), 3, 7);
423 
    return 0;
424 
}
425 
 
426 
int ceata_check_error()
427 
{
428 
    uint32_t status, error;
429 
    PASS_RC(mmc_fastio_read(0xf, &status), 2, 0);
430 
    if (status & 1)
431 
    {
432 
        PASS_RC(mmc_fastio_read(0x9, &error), 2, 1);
433 
        RET_ERR((error << 2) | 2);
434 
    }
435 
    return 0;
436 
}
437 
 
438 
int ceata_wait_idle()
439 
{
440 
    long startusec = USEC_TIMER;
441 
    while (true)
442 
    {
443 
        uint32_t status;
444 
        PASS_RC(mmc_fastio_read(0xf, &status), 1, 0);
445 
        if (!(status & 0x88)) return 0;
446 
        if (TIMEOUT_EXPIRED(startusec, CEATA_DAT_NONBUSY_TIMEOUT)) RET_ERR(1);
447 
        sleep(50000);
448 
    }
449 
}
450 
 
451 
int ceata_cancel_command()
452 
{
453 
    *((uint32_t volatile*)0x3cf00200) = 0x9000e;
454 
    sleep(1);
455 
    *((uint32_t volatile*)0x3cf00200) = 0x9000f;
456 
    sleep(1);
457 
    *((uint32_t volatile*)0x3cf00200) = 0x90003;
458 
    sleep(1);
459 
    PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_STOP_TRANSMISSION)
460 
                           | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1 | SDCI_CMD_RES_BUSY
461 
                           | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
462 
                             0, NULL, CEATA_COMMAND_TIMEOUT), 1, 0);
463 
    PASS_RC(ceata_wait_idle(), 1, 1);
464 
    return 0;
465 
}
466 
 
467 
int ceata_rw_multiple_block(bool write, void* buf, uint32_t count, long timeout)
468 
{
469 
    mmc_discard_irq();
470 
    uint32_t responsetype;
471 
    uint32_t cmdtype;
472 
    uint32_t direction;
473 
    if (write)
474 
    {
475 
        cmdtype = SDCI_CMD_CMD_TYPE_ADTC | SDCI_CMD_CMD_RD_WR;
476 
        responsetype = SDCI_CMD_RES_TYPE_R1 | SDCI_CMD_RES_BUSY;
477 
        direction = MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_WRITE;
478 
    }
479 
    else
480 
    {
481 
        cmdtype = SDCI_CMD_CMD_TYPE_ADTC;
482 
        responsetype = SDCI_CMD_RES_TYPE_R1;
483 
        direction = MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_READ;
484 
    }
485 
    SDCI_DMASIZE = 0x200;
486 
    SDCI_DMAADDR = buf;
487 
    SDCI_DMACOUNT = count;
488 
    SDCI_DCTRL = SDCI_DCTRL_TXFIFORST | SDCI_DCTRL_RXFIFORST;
636 theseven 489 
    invalidate_dcache();
629 theseven 490 
    PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_BLOCK)
491 
                           | SDCI_CMD_CMD_TYPE_ADTC | cmdtype | responsetype
492 
                           | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
493 
                             direction | MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_COUNT(count),
494 
                             NULL, CEATA_COMMAND_TIMEOUT), 4, 0);
495 
    if (write) SDCI_DCTRL = SDCI_DCTRL_TRCONT_TX;
496 
    if (wakeup_wait(&mmc_wakeup, timeout) == THREAD_TIMEOUT)
497 
    {
498 
        PASS_RC(ceata_cancel_command(), 4, 1);
499 
        RET_ERR(2);
500 
    }
501 
    PASS_RC(mmc_dsta_check_data_success(), 4, 3);
502 
    if (wakeup_wait(&mmc_comp_wakeup, timeout) == THREAD_TIMEOUT)
503 
    {
504 
        PASS_RC(ceata_cancel_command(), 4, 4);
505 
        RET_ERR(4);
506 
    }
507 
    PASS_RC(ceata_check_error(), 4, 5);
508 
    return 0;
509 
}
510 
 
301 theseven 511 
int ata_identify(uint16_t* buf)
512 
{
513 
    int i;
629 theseven 514 
    if (ceata)
301 theseven 515 
    {
629 theseven 516 
        memset(ceata_taskfile, 0, 16);
517 
        ceata_taskfile[0xf] = 0xec;
518 
        PASS_RC(ceata_wait_idle(), 2, 0);
519 
        PASS_RC(ceata_write_multiple_register(0, ceata_taskfile, 16), 2, 1);
520 
        PASS_RC(ceata_rw_multiple_block(false, buf, 1, CEATA_COMMAND_TIMEOUT), 2, 2);
301 theseven 521 
    }
629 theseven 522 
    else
523 
    {
524 
        PASS_RC(ata_wait_for_not_bsy(10000000), 1, 0);
525 
        ata_write_cbr(&ATA_PIO_DVR, 0);
526 
        ata_write_cbr(&ATA_PIO_CSD, 0xec);
527 
        PASS_RC(ata_wait_for_start_of_transfer(10000000), 1, 1);
528 
        for (i = 0; i < 0x100; i++)
529 
        {
530 
            uint16_t word = ata_read_cbr(&ATA_PIO_DTR);
531 
            buf[i] = (word >> 8) | (word << 8);
532 
        }
533 
    }
534 
    return 0;
301 theseven 535 
}
536 
 
537 
void ata_set_active(void)
538 
{
539 
    ata_last_activity_value = USEC_TIMER;
540 
}
541 
 
620 theseven 542 
bool ata_disk_is_active(void)
543 
{
544 
    return ata_powered;
545 
}
546 
 
547 
int ata_num_drives(void)
548 
{
549 
    return 1;
550 
}
551 
 
317 theseven 552 
int ata_set_feature(uint32_t feature, uint32_t param)
553 
{
554 
    PASS_RC(ata_wait_for_rdy(500000), 1, 0);
555 
    ata_write_cbr(&ATA_PIO_DVR, 0);
556 
    ata_write_cbr(&ATA_PIO_FED, 3);
557 
    ata_write_cbr(&ATA_PIO_SCR, param);
558 
    ata_write_cbr(&ATA_PIO_CSD, feature);
559 
    PASS_RC(ata_wait_for_rdy(500000), 1, 1);
560 
    return 0;
561 
}
562 
 
301 theseven 563 
int ata_power_up()
564 
{
565 
    ata_set_active();
357 theseven 566 
    if (ata_powered) return 0;
301 theseven 567 
    i2c_sendbyte(0, 0xe6, 0x1b, 1);
629 theseven 568 
    if (ceata)
301 theseven 569 
    {
629 theseven 570 
        clockgate_enable(9, true);
571 
        SDCI_RESET = 0xa5;
572 
        sleep(1000);
573 
        *((uint32_t volatile*)0x3cf00380) = 0;
574 
        *((uint32_t volatile*)0x3cf0010c) = 0xff;
575 
        SDCI_CTRL = SDCI_CTRL_SDCIEN | SDCI_CTRL_CLK_SEL_SDCLK
576 
                  | SDCI_CTRL_BIT_8 | SDCI_CTRL_BIT_14;
577 
        SDCI_CDIV = SDCI_CDIV_CLKDIV(260);
578 
        *((uint32_t volatile*)0x3cf00200) = 0xb000f;
579 
        SDCI_IRQ_MASK = SDCI_IRQ_MASK_MASK_DAT_DONE_INT | SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT;
580 
        PASS_RC(mmc_init(), 2, 0);
581 
        SDCI_CDIV = SDCI_CDIV_CLKDIV(4);
582 
        sleep(10000);
583 
        PASS_RC(ceata_init(8), 2, 1);
584 
        PASS_RC(ata_identify(ata_identify_data), 2, 2);
301 theseven 585 
    }
629 theseven 586 
    else
301 theseven 587 
    {
629 theseven 588 
        clockgate_enable(5, true);
589 
        ATA_CFG = BIT(0);
590 
        sleep(1000);
591 
        ATA_CFG = 0;
592 
        sleep(6000);
593 
        ATA_SWRST = BIT(0);
594 
        sleep(500);
595 
        ATA_SWRST = 0;
596 
        sleep(90000);
597 
        ATA_CONTROL = BIT(0);
598 
        sleep(200000);
599 
        ATA_PIO_TIME = 0x191f7;
600 
        ATA_PIO_LHR = 0;
601 
        while (!(ATA_PIO_READY & BIT(1))) sleep(100);
602 
        PASS_RC(ata_identify(ata_identify_data), 2, 0);
603 
        uint32_t piotime = 0x11f3;
604 
        uint32_t mdmatime = 0x1c175;
605 
        uint32_t udmatime = 0x5071152;
606 
        uint32_t param = 0;
607 
        ata_dma_flags = 0;
608 
        ata_lba48 = ata_identify_data[83] & BIT(10) ? true : false;
609 
        if (ata_identify_data[53] & BIT(1))
301 theseven 610 
        {
629 theseven 611 
            if (ata_identify_data[64] & BIT(1)) piotime = 0x2072;
612 
            else if (ata_identify_data[64] & BIT(0)) piotime = 0x7083;
301 theseven 613 
        }
629 theseven 614 
        if (ata_identify_data[63] & BIT(2))
301 theseven 615 
        {
629 theseven 616 
            mdmatime = 0x5072;
617 
            param = 0x22;
301 theseven 618 
        }
629 theseven 619 
        else if (ata_identify_data[63] & BIT(1))
301 theseven 620 
        {
629 theseven 621 
            mdmatime = 0x7083;
622 
            param = 0x21;
301 theseven 623 
        }
629 theseven 624 
        if (ata_identify_data[63] & BITRANGE(0, 2))
301 theseven 625 
        {
629 theseven 626 
            ata_dma_flags = BIT(3) | BIT(10);
627 
            param |= 0x20;
301 theseven 628 
        }
629 theseven 629 
        if (ata_identify_data[53] & BIT(2))
301 theseven 630 
        {
629 theseven 631 
            if (ata_identify_data[88] & BIT(4))
632 
            {
633 
                udmatime = 0x2010a52;
634 
                param = 0x44;
635 
            }
636 
            else if (ata_identify_data[88] & BIT(3))
637 
            {
638 
                udmatime = 0x2020a52;
639 
                param = 0x43;
640 
            }
641 
            else if (ata_identify_data[88] & BIT(2))
642 
            {
643 
                udmatime = 0x3030a52;
644 
                param = 0x42;
645 
            }
646 
            else if (ata_identify_data[88] & BIT(1))
647 
            {
648 
                udmatime = 0x3050a52;
649 
                param = 0x41;
650 
            }
651 
            if (ata_identify_data[88] & BITRANGE(0, 4))
652 
            {
653 
                ata_dma_flags = BIT(2) | BIT(3) | BIT(9) | BIT(10);
654 
                param |= 0x40;
655 
            }
301 theseven 656 
        }
629 theseven 657 
        ata_dma = param ? true : false;
658 
        PASS_RC(ata_set_feature(0xef, param), 2, 1);
659 
        if (ata_identify_data[82] & BIT(5)) PASS_RC(ata_set_feature(0x02, 0), 2, 2);
660 
        if (ata_identify_data[82] & BIT(6)) PASS_RC(ata_set_feature(0x55, 0), 2, 3);
661 
        ATA_PIO_TIME = piotime;
662 
        ATA_MDMA_TIME = mdmatime;
663 
        ATA_UDMA_TIME = udmatime;
301 theseven 664 
    }
629 theseven 665 
    if (ata_lba48)
666 
        ata_total_sectors = ata_identify_data[100]
667 
                            | (((uint64_t)ata_identify_data[101]) << 16)
668 
                            | (((uint64_t)ata_identify_data[102]) << 32)
669 
                            | (((uint64_t)ata_identify_data[103]) << 48);
670 
    else ata_total_sectors = ata_identify_data[60] | (((uint32_t)ata_identify_data[61]) << 16);
671 
    ata_total_sectors >>= 3;
301 theseven 672 
    ata_powered = true;
673 
    ata_set_active();
674 
    return 0;
675 
}
676 
 
677 
void ata_power_down()
678 
{
357 theseven 679 
    if (!ata_powered) return;
301 theseven 680 
    ata_powered = false;
629 theseven 681 
    if (ceata)
682 
    {
683 
        memset(ceata_taskfile, 0, 16);
684 
        ceata_taskfile[0xf] = 0xe0;
685 
        ceata_wait_idle();
686 
        ceata_write_multiple_register(0, ceata_taskfile, 16);
687 
        wakeup_wait(&mmc_comp_wakeup, CEATA_COMMAND_TIMEOUT);
688 
        sleep(30000);
689 
        clockgate_enable(9, false);
690 
    }
691 
    else
692 
    {
693 
        ata_wait_for_rdy(1000000);
694 
        ata_write_cbr(&ATA_PIO_DVR, 0);
695 
        ata_write_cbr(&ATA_PIO_CSD, 0xe0);
696 
        ata_wait_for_rdy(1000000);
697 
        sleep(30000);
698 
        ATA_CONTROL = 0;
699 
        while (!(ATA_CONTROL & BIT(1))) yield();
700 
        clockgate_enable(5, false);
701 
    }
301 theseven 702 
    i2c_sendbyte(0, 0xe6, 0x1b, 0);
703 
}
704 
 
337 theseven 705 
int ata_rw_chunk(uint64_t sector, uint32_t cnt, void* buffer, bool write)
706 
{
629 theseven 707 
    if (ceata)
337 theseven 708 
    {
629 theseven 709 
        memset(ceata_taskfile, 0, 16);
710 
        ceata_taskfile[0x2] = cnt >> 5;
711 
        ceata_taskfile[0x3] = sector >> 21;
712 
        ceata_taskfile[0x4] = sector >> 29;
713 
        ceata_taskfile[0x5] = sector >> 37;
714 
        ceata_taskfile[0xa] = cnt << 3;
715 
        ceata_taskfile[0xb] = sector << 3;
716 
        ceata_taskfile[0xc] = sector >> 5;
717 
        ceata_taskfile[0xd] = sector >> 13;
718 
        ceata_taskfile[0xf] = write ? 0x35 : 0x25;
719 
        PASS_RC(ceata_wait_idle(), 2, 0);
720 
        PASS_RC(ceata_write_multiple_register(0, ceata_taskfile, 16), 2, 1);
721 
        PASS_RC(ceata_rw_multiple_block(write, buffer, cnt, CEATA_COMMAND_TIMEOUT), 2, 2);
337 theseven 722 
    }
723 
    else
724 
    {
629 theseven 725 
        PASS_RC(ata_wait_for_rdy(100000), 2, 0);
726 
        ata_write_cbr(&ATA_PIO_DVR, 0);
727 
        if (ata_lba48)
337 theseven 728 
        {
629 theseven 729 
            ata_write_cbr(&ATA_PIO_SCR, cnt >> 5);
730 
            ata_write_cbr(&ATA_PIO_SCR, (cnt << 3) & 0xff);
731 
            ata_write_cbr(&ATA_PIO_LHR, (sector >> 37) & 0xff);
732 
            ata_write_cbr(&ATA_PIO_LMR, (sector >> 29) & 0xff);
733 
            ata_write_cbr(&ATA_PIO_LLR, (sector >> 21) & 0xff);
734 
            ata_write_cbr(&ATA_PIO_LHR, (sector >> 13) & 0xff);
735 
            ata_write_cbr(&ATA_PIO_LMR, (sector >> 5) & 0xff);
736 
            ata_write_cbr(&ATA_PIO_LLR, (sector << 3) & 0xff);
737 
            ata_write_cbr(&ATA_PIO_DVR, BIT(6));
738 
            if (write) ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0x35 : 0x39);
739 
            else ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0x25 : 0x29);
337 theseven 740 
        }
741 
        else
742 
        {
629 theseven 743 
            ata_write_cbr(&ATA_PIO_SCR, (cnt << 3) & 0xff);
744 
            ata_write_cbr(&ATA_PIO_LHR, (sector >> 13) & 0xff);
745 
            ata_write_cbr(&ATA_PIO_LMR, (sector >> 5) & 0xff);
746 
            ata_write_cbr(&ATA_PIO_LLR, (sector << 3) & 0xff);
747 
            ata_write_cbr(&ATA_PIO_DVR, BIT(6) | ((sector >> 21) & 0xf));
748 
            if (write) ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0xca : 0x30);
749 
            else ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0xc8 : 0xc4);
337 theseven 750 
        }
629 theseven 751 
        if (ata_dma)
337 theseven 752 
        {
629 theseven 753 
            PASS_RC(ata_wait_for_start_of_transfer(500000), 2, 1);
754 
            if (write)
755 
            {
756 
                ATA_SBUF_START = buffer;
757 
                ATA_SBUF_SIZE = SECTOR_SIZE * cnt;
758 
                ATA_CFG |= BIT(4);
759 
            }
760 
            else
761 
            {
762 
                ATA_TBUF_START = buffer;
763 
                ATA_TBUF_SIZE = SECTOR_SIZE * cnt;
764 
                ATA_CFG &= ~BIT(4);
765 
            }
766 
            ATA_XFR_NUM = SECTOR_SIZE * cnt - 1;
767 
            ATA_CFG |= ata_dma_flags;
768 
            ATA_CFG &= ~(BIT(7) | BIT(8));
769 
            wakeup_wait(&ata_wakeup, TIMEOUT_NONE);
770 
            ATA_IRQ = BITRANGE(0, 4);
771 
            ATA_IRQ_MASK = BIT(0);
772 
            ATA_COMMAND = BIT(0);
773 
            if (wakeup_wait(&ata_wakeup, 500000) == THREAD_TIMEOUT)
774 
            {
775 
                ATA_COMMAND = BIT(1);
776 
                ATA_CFG &= ~(BITRANGE(2, 3) | BIT(12));
777 
                RET_ERR(2);
778 
            }
337 theseven 779 
            ATA_COMMAND = BIT(1);
780 
            ATA_CFG &= ~(BITRANGE(2, 3) | BIT(12));
781 
        }
629 theseven 782 
        else
337 theseven 783 
        {
629 theseven 784 
            cnt *= SECTOR_SIZE / 512;
785 
            while (cnt--)
786 
            {
787 
                int i;
788 
                PASS_RC(ata_wait_for_start_of_transfer(500000), 2, 1);
789 
                if (write)
790 
                    for (i = 0; i < 256; i++)
791 
                        ata_write_cbr(&ATA_PIO_DTR, ((uint16_t*)buffer)[i]);
792 
                else
793 
                    for (i = 0; i < 256; i++)
794 
                        ((uint16_t*)buffer)[i] = ata_read_cbr(&ATA_PIO_DTR);
795 
                buffer += 512;
796 
            }
337 theseven 797 
        }
629 theseven 798 
        PASS_RC(ata_wait_for_end_of_transfer(100000), 2, 3);
337 theseven 799 
    }
800 
    return 0;
801 
}
802 
 
613 theseven 803 
#ifdef ATA_HAVE_BBT
804 
int ata_bbt_translate(uint64_t sector, uint32_t count, uint64_t* phys, uint32_t* physcount)
805 
{
806 
    if (sector + count > ata_virtual_sectors) RET_ERR(0);
807 
    if (!ata_bbt)
808 
    {
809 
        *phys = sector;
810 
        *physcount = count;
811 
        return 0;
812 
    }
813 
    if (!count)
814 
    {
815 
        *phys = 0;
816 
        *physcount = 0;
817 
        return 0;
818 
    }
819 
    uint32_t offset;
820 
    uint32_t l0idx = sector >> 15;
821 
    uint32_t l0offs = sector & 0x7fff;
822 
    *physcount = MIN(count, 0x8000 - l0offs);
823 
    uint32_t l0data = ata_bbt[0][l0idx << 1];
824 
    uint32_t base = ata_bbt[0][(l0idx << 1) | 1] << 12;
825 
    if (l0data < 0x8000) offset = l0data + base;
826 
    else
827 
    {
828 
        uint32_t l1idx = (sector >> 10) & 0x1f;
829 
        uint32_t l1offs = sector & 0x3ff;
830 
        *physcount = MIN(count, 0x400 - l1offs);
831 
        uint32_t l1data = ata_bbt[l0data & 0x7fff][l1idx];
832 
        if (l1data < 0x8000) offset = l1data + base;
833 
        else
834 
        {
835 
            uint32_t l2idx = (sector >> 5) & 0x1f;
836 
            uint32_t l2offs = sector & 0x1f;
837 
            *physcount = MIN(count, 0x20 - l2offs);
838 
            uint32_t l2data = ata_bbt[l1data & 0x7fff][l2idx];
839 
            if (l2data < 0x8000) offset = l2data + base;
840 
            else
841 
            {
842 
                uint32_t l3idx = sector & 0x1f;
843 
                uint32_t l3data = ata_bbt[l2data & 0x7fff][l3idx];
844 
                for (*physcount = 1; *physcount < count && l3idx + *physcount < 0x20; *physcount++)
845 
                    if (ata_bbt[l2data & 0x7fff][l3idx + *physcount] != l3data)
846 
                        break;
847 
                offset = l3data + base;
848 
            }
849 
        }
850 
    }
851 
    *phys = sector + offset;
852 
    return 0;
853 
}
854 
#endif
855 
 
301 theseven 856 
int ata_rw_sectors(uint64_t sector, uint32_t count, void* buffer, bool write)
857 
{
627 theseven 858 
    if (((uint32_t)buffer) & (CACHEALIGN_SIZE - 1))
859 
        panicf(PANIC_KILLTHREAD,
860 
               "ATA: Misaligned data buffer at %08X (sector %lu, count %lu)",
861 
               (unsigned int)buffer, (unsigned int)sector, count);
328 theseven 862 
#ifdef ATA_HAVE_BBT
863 
    if (sector + count > ata_virtual_sectors) RET_ERR(0);
430 theseven 864 
    if (ata_bbt)
865 
        while (count)
328 theseven 866 
        {
613 theseven 867 
            uint64_t phys;
868 
            uint32_t cnt;
869 
            PASS_RC(ata_bbt_translate(sector, count, &phys, &cnt), 0, 0);
870 
            uint32_t offset = phys - sector;
430 theseven 871 
            if (offset != ata_last_offset && phys - ata_last_phys < 64) ata_soft_reset();
872 
            ata_last_offset = offset;
873 
            ata_last_phys = phys + cnt;
874 
            PASS_RC(ata_rw_sectors_internal(phys, cnt, buffer, write), 0, 0);
875 
            buffer += cnt * SECTOR_SIZE;
876 
            sector += cnt;
877 
            count -= cnt;
328 theseven 878 
        }
430 theseven 879 
    else PASS_RC(ata_rw_sectors_internal(sector, count, buffer, write), 0, 0);
328 theseven 880 
    return 0;
881 
}
882 
 
883 
int ata_rw_sectors_internal(uint64_t sector, uint32_t count, void* buffer, bool write)
884 
{
885 
#endif
301 theseven 886 
    if (sector + count > ata_total_sectors) RET_ERR(0);
887 
    if (!ata_powered) ata_power_up();
888 
    ata_set_active();
889 
    if (ata_dma && write) clean_dcache();
890 
    else if (ata_dma) invalidate_dcache();
629 theseven 891 
    if (!ceata) ATA_COMMAND = BIT(1);
301 theseven 892 
    while (count)
893 
    {
317 theseven 894 
        uint32_t cnt = MIN(ata_lba48 ? 8192 : 32, count);
337 theseven 895 
        int rc = -1;
613 theseven 896 
        rc = ata_rw_chunk(sector, cnt, buffer, write);
620 theseven 897 
        if (rc && ata_error_srst) ata_soft_reset();
898 
        if (rc && ata_retries)
301 theseven 899 
        {
337 theseven 900 
            void* buf = buffer;
405 theseven 901 
            uint64_t sect;
337 theseven 902 
            for (sect = sector; sect < sector + cnt; sect++)
903 
            {
904 
                rc = -1;
620 theseven 905 
                int tries = ata_retries;
337 theseven 906 
                while (tries-- && rc)
907 
                {
908 
                    rc = ata_rw_chunk(sect, 1, buf, write);
620 theseven 909 
                    if (rc && ata_error_srst) ata_soft_reset();
337 theseven 910 
                }
911 
                if (rc) break;
912 
                buf += SECTOR_SIZE;
913 
            }
301 theseven 914 
        }
337 theseven 915 
        PASS_RC(rc, 1, 1);
916 
        buffer += SECTOR_SIZE * cnt;
301 theseven 917 
        sector += cnt;
918 
        count -= cnt;
919 
    }
920 
    ata_set_active();
921 
    return 0;
922 
}
923 
 
924 
static void ata_thread(void)
925 
{
926 
    while (true)
927 
    {
928 
        mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
929 
        if (TIME_AFTER(USEC_TIMER, ata_last_activity_value + ata_sleep_timeout) && ata_powered)
930 
            ata_power_down();
931 
        mutex_unlock(&ata_mutex);
932 
        sleep(1000000);
933 
    }
934 
}
935 
 
936 
/* API Functions */
937 
int ata_soft_reset()
938 
{
629 theseven 939 
    int rc;
301 theseven 940 
    mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
941 
    if (!ata_powered) ata_power_up();
942 
    ata_set_active();
629 theseven 943 
    if (ceata) rc = ceata_soft_reset();
944 
    else
945 
    {
946 
        ata_write_cbr(&ATA_PIO_DAD, BIT(1) | BIT(2));
947 
        sleep(10);
948 
        ata_write_cbr(&ATA_PIO_DAD, 0);
949 
        rc = ata_wait_for_rdy(20000000);
950 
    }
613 theseven 951 
    if (IS_ERR(rc))
952 
    {
953 
        ata_power_down();
954 
        sleep(3000000);
955 
        ata_power_up();
956 
    }
301 theseven 957 
    ata_set_active();
958 
    mutex_unlock(&ata_mutex);
620 theseven 959 
    return rc;
301 theseven 960 
}
961 
 
962 
int ata_read_sectors(IF_MD2(int drive,) unsigned long start, int incount,
963 
                     void* inbuf)
964 
{
965 
    mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
337 theseven 966 
    int rc = ata_rw_sectors(start, incount, inbuf, false);
301 theseven 967 
    mutex_unlock(&ata_mutex);
968 
    return rc;
969 
}
970 
 
971 
int ata_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
972 
                      const void* outbuf)
973 
{
974 
    mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
337 theseven 975 
    int rc = ata_rw_sectors(start, count, (void*)((uint32_t)outbuf), true);
301 theseven 976 
    mutex_unlock(&ata_mutex);
977 
    return rc;
978 
}
979 
 
337 theseven 980 
void ata_spindown(int seconds)
981 
{
982 
    ata_sleep_timeout = seconds * 1000000;
983 
}
301 theseven 984 
 
985 
void ata_sleep(void)
986 
{
987 
    mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
988 
    ata_power_down();
989 
    mutex_unlock(&ata_mutex);
990 
}
991 
 
992 
void ata_sleepnow(void)
993 
{
994 
    ata_sleep();
995 
}
996 
 
997 
void ata_close(void)
998 
{
999 
    ata_sleep();
1000 
}
1001 
 
1002 
void ata_spin(void)
1003 
{
1004 
    ata_power_up();
1005 
}
1006 
 
1007 
void ata_get_info(IF_MD2(int drive,) struct storage_info *info)
1008 
{
1009 
    (*info).sector_size = SECTOR_SIZE;
328 theseven 1010 
#ifdef ATA_HAVE_BBT
1011 
    (*info).num_sectors = ata_virtual_sectors;
1012 
#else
301 theseven 1013 
    (*info).num_sectors = ata_total_sectors;
328 theseven 1014 
#endif
301 theseven 1015 
    (*info).vendor = "Apple";
1016 
    (*info).product = "iPod Classic";
1017 
    (*info).revision = "1.0";
613 theseven 1018 
    (*info).driverinfo = &drvinfo;
301 theseven 1019 
}
1020 
 
1021 
long ata_last_disk_activity(void)
1022 
{
1023 
    return ata_last_activity_value;
1024 
}
1025 
 
613 theseven 1026 
#ifdef ATA_HAVE_BBT
1027 
void ata_bbt_disable()
301 theseven 1028 
{
328 theseven 1029 
    mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
613 theseven 1030 
    if (ata_bbt) free(ata_bbt);
430 theseven 1031 
    ata_bbt = NULL;
613 theseven 1032 
    ata_virtual_sectors = ata_total_sectors;
1033 
    mutex_unlock(&ata_mutex);
1034 
}
1035 
 
1036 
void ata_bbt_reload()
1037 
{
1038 
    mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
1039 
    ata_bbt_disable();
328 theseven 1040 
    ata_power_up();
430 theseven 1041 
    uint32_t* buf = (uint32_t*)memalign(0x10, 0x1000);
1042 
    if (buf)
328 theseven 1043 
    {
620 theseven 1044 
        if (IS_ERR(ata_bbt_read_sectors(0, 1, buf)))
1045 
            ata_virtual_sectors = ata_total_sectors;
1046 
        else if (!memcmp(buf, "emBIbbth", 8))
328 theseven 1047 
        {
430 theseven 1048 
            ata_virtual_sectors = (((uint64_t)buf[0x1fd]) << 32) | buf[0x1fc];
1049 
            uint32_t count = buf[0x1ff];
1050 
            ata_bbt = (typeof(ata_bbt))memalign(0x10, 0x1000 * count);
620 theseven 1051 
            if (!ata_bbt)
430 theseven 1052 
            {
620 theseven 1053 
                cprintf(CONSOLE_BOOT, "ATA: Failed to allocate memory for BBT! (%d bytes)",
1054 
                        0x1000 * count);
1055 
                ata_virtual_sectors = ata_total_sectors;
1056 
            }
1057 
            else
1058 
            {
1059 
                uint32_t i;
1060 
                uint32_t cnt;
1061 
                for (i = 0; i < count; i += cnt)
1062 
                {
1063 
                    uint32_t phys = buf[0x200 + i];
1064 
                    for (cnt = 1; cnt < count; cnt++)
1065 
                        if (buf[0x200 + i + cnt] != phys + cnt)
1066 
                            break;
1067 
                    if (IS_ERR(ata_bbt_read_sectors(phys, cnt, ata_bbt[i << 6])))
1068 
                    {
1069 
                        free(ata_bbt);
1070 
                        ata_virtual_sectors = ata_total_sectors;
430 theseven 1071 
                        break;
620 theseven 1072 
                    }
1073 
                }
1074 
                if (ata_bbt) reownalloc(ata_bbt, NULL);
430 theseven 1075 
            }
328 theseven 1076 
        }
430 theseven 1077 
        else ata_virtual_sectors = ata_total_sectors;
1078 
        free(buf);
328 theseven 1079 
    }
437 theseven 1080 
    else ata_virtual_sectors = ata_total_sectors;
328 theseven 1081 
    mutex_unlock(&ata_mutex);
613 theseven 1082 
}
328 theseven 1083 
#endif
613 theseven 1084 
 
1085 
int ata_init(void)
1086 
{
1087 
    mutex_init(&ata_mutex);
1088 
    wakeup_init(&ata_wakeup);
629 theseven 1089 
    wakeup_init(&mmc_wakeup);
1090 
    wakeup_init(&mmc_comp_wakeup);
1091 
    ceata = PDAT(11) & BIT(1);
1092 
    if (ceata)
1093 
    {
1094 
        ata_lba48 = true;
1095 
        ata_dma = true;
1096 
        PCON(8) = 0x33333333;
1097 
        PCON(9) = (PCON(9) & ~0xff) | 0x33;
1098 
        PCON(11) |= 0xf;
1099 
        *((uint32_t volatile*)0x38a00000) = 0;
1100 
        *((uint32_t volatile*)0x38700000) = 0;
1101 
    }
1102 
    else
1103 
    {
1104 
        PCON(7) = 0x44444444;
1105 
        PCON(8) = 0x44444444;
1106 
        PCON(9) = 0x44444444;
1107 
        PCON(10) = (PCON(10) & ~0xffff) | 0x4444;
1108 
    }
613 theseven 1109 
    ata_powered = false;
1110 
    ata_total_sectors = 0;
1111 
#ifdef ATA_HAVE_BBT
1112 
    ata_bbt_reload();
1113 
#endif
429 theseven 1114 
    thread_create(&ata_thread_handle, "ATA idle monitor", ata_thread, ata_stack,
543 theseven 1115 
                  sizeof(ata_stack), OS_THREAD, 1, true);
301 theseven 1116 
    return 0;
1117 
}
1118 
 
1119 
#ifdef CONFIG_STORAGE_MULTI
1120 
int ata_num_drives(int first_drive)
1121 
{
1122 
    /* We don't care which logical drive number(s) we have been assigned */
1123 
    (void)first_drive;
1124 
 
1125 
    return 1;
1126 
}
1127 
#endif
1128 
 
1129 
void INT_ATA()
1130 
{
1131 
    uint32_t ata_irq = ATA_IRQ;
1132 
    ATA_IRQ = ata_irq;
1133 
    if (ata_irq & ATA_IRQ_MASK) wakeup_signal(&ata_wakeup);
1134 
    ATA_IRQ_MASK = 0;
1135 
}
629 theseven 1136 
 
1137 
void INT_MMC()
1138 
{
1139 
    uint32_t irq = SDCI_IRQ;
1140 
    if (irq & SDCI_IRQ_DAT_DONE_INT) wakeup_signal(&mmc_wakeup);
1141 
    if (irq & SDCI_IRQ_IOCARD_IRQ_INT) wakeup_signal(&mmc_comp_wakeup);
1142 
    SDCI_IRQ = irq;
1143 
}