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301 theseven 1 
/***************************************************************************
2 
 *             __________               __   ___.
3 
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
4 
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
5 
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
6 
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
7 
 *                     \/            \/     \/    \/            \/
8 
 * $Id$
9 
 *
10 
 * Copyright (C) 2007 Dave Chapman
11 
 *
12 
 * This program is free software; you can redistribute it and/or
13 
 * modify it under the terms of the GNU General Public License
14 
 * as published by the Free Software Foundation; either version 2
15 
 * of the License, or (at your option) any later version.
16 
 *
17 
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 
 * KIND, either express or implied.
19 
 *
20 
 ****************************************************************************/
21 
#include "global.h"
22 
#include "thread.h"
23 
#include "disk.h"
24 
#include "storage.h"
25 
#include "timer.h"
26 
#include "../ipodnano3g/s5l8702.h"
27 
 
28 
/** static, private data **/
29 
uint16_t ata_identify_data[0x100];
30 
bool ata_lba48;
31 
bool ata_dma;
32 
uint64_t ata_total_sectors;
33 
static struct mutex ata_mutex;
34 
static struct wakeup ata_wakeup;
35 
static uint32_t ata_dma_flags;
36 
static long ata_last_activity_value = -1;
37 
static long ata_sleep_timeout = 20000000;
38 
static uint32_t ata_stack[0x80];
39 
static bool ata_powered;
40 
 
41 
 
42 
static uint16_t ata_read_cbr(uint32_t volatile* reg)
43 
{
317 theseven 44 
    while (!(ATA_PIO_READY & 2)) yield();
301 theseven 45 
    volatile uint32_t dummy = *reg;
317 theseven 46 
    while (!(ATA_PIO_READY & 1)) yield();
301 theseven 47 
    return ATA_PIO_RDATA;
48 
}
49 
 
50 
static void ata_write_cbr(uint32_t volatile* reg, uint16_t data)
51 
{
317 theseven 52 
    while (!(ATA_PIO_READY & 2)) yield();
301 theseven 53 
    *reg = data;
54 
}
55 
 
56 
static int ata_wait_for_not_bsy(long timeout)
57 
{
58 
    long startusec = USEC_TIMER;
59 
    while (true)
60 
    {
61 
        uint8_t csd = ata_read_cbr(&ATA_PIO_CSD);
62 
        if (!(csd & BIT(7))) return 0;
63 
        if (TIMEOUT_EXPIRED(startusec, timeout)) RET_ERR(0);
64 
    }
65 
}
66 
 
67 
static int ata_wait_for_rdy(long timeout)
68 
{
69 
    long startusec = USEC_TIMER;
70 
    PASS_RC(ata_wait_for_not_bsy(timeout), 1, 0);
71 
    while (true)
72 
    {
73 
        uint8_t dad = ata_read_cbr(&ATA_PIO_DAD);
74 
        if (dad & BIT(6)) return 0;
75 
        if (TIMEOUT_EXPIRED(startusec, timeout)) RET_ERR(1);
76 
    }
77 
}
78 
 
79 
static int ata_wait_for_start_of_transfer(long timeout)
80 
{
81 
    long startusec = USEC_TIMER;
82 
    PASS_RC(ata_wait_for_not_bsy(timeout), 2, 0);
83 
    while (true)
84 
    {
85 
        uint8_t dad = ata_read_cbr(&ATA_PIO_DAD);
86 
        if (dad & BIT(0)) RET_ERR(1);
87 
        if ((dad & (BIT(7) | BIT(3))) == BIT(3)) return 0;
88 
        if (TIMEOUT_EXPIRED(startusec, timeout)) RET_ERR(2);
89 
    }
90 
}
91 
 
92 
static int ata_wait_for_end_of_transfer(long timeout)
93 
{
94 
    PASS_RC(ata_wait_for_not_bsy(timeout), 2, 0);
95 
    uint8_t dad = ata_read_cbr(&ATA_PIO_DAD);
96 
    if (dad & BIT(0)) RET_ERR(1);
97 
    if ((dad & (BIT(3) | BITRANGE(5, 7))) == BIT(6)) return 0;
98 
    RET_ERR(2);
99 
}
100 
 
101 
int ata_identify(uint16_t* buf)
102 
{
103 
    int i;
104 
    PASS_RC(ata_wait_for_not_bsy(10000000), 1, 0);
105 
    ata_write_cbr(&ATA_PIO_DVR, 0);
106 
    ata_write_cbr(&ATA_PIO_CSD, 0xec);
107 
    PASS_RC(ata_wait_for_start_of_transfer(10000000), 1, 1);
108 
    for (i = 0; i < 0x100; i++)
109 
    {
110 
        uint16_t word = ata_read_cbr(&ATA_PIO_DTR);
111 
        buf[i] = (word >> 8) | (word << 8);
112 
    }
113 
}
114 
 
115 
void ata_set_active(void)
116 
{
117 
    ata_last_activity_value = USEC_TIMER;
118 
}
119 
 
317 theseven 120 
int ata_set_feature(uint32_t feature, uint32_t param)
121 
{
122 
    PASS_RC(ata_wait_for_rdy(500000), 1, 0);
123 
    ata_write_cbr(&ATA_PIO_DVR, 0);
124 
    ata_write_cbr(&ATA_PIO_FED, 3);
125 
    ata_write_cbr(&ATA_PIO_SCR, param);
126 
    ata_write_cbr(&ATA_PIO_CSD, feature);
127 
    PASS_RC(ata_wait_for_rdy(500000), 1, 1);
128 
    return 0;
129 
}
130 
 
301 theseven 131 
int ata_power_up()
132 
{
133 
    ata_set_active();
134 
    i2c_sendbyte(0, 0xe6, 0x1b, 1);
135 
    clockgate_enable(5, true);
136 
    ATA_CFG = BIT(0);
137 
    sleep(1000);
138 
    ATA_CFG = 0;
139 
    sleep(6000);
140 
    ATA_SWRST = BIT(0);
141 
    sleep(500);
142 
    ATA_SWRST = 0;
143 
    sleep(90000);
144 
    ATA_CONTROL = BIT(0);
145 
    sleep(200000);
146 
    ATA_PIO_TIME = 0x191f7;
147 
    ATA_PIO_LHR = 0;
148 
    while (!(ATA_PIO_READY & BIT(1))) sleep(100);
149 
    PASS_RC(ata_identify(ata_identify_data), 2, 0);
150 
    uint32_t piotime = 0x11f3;
151 
    uint32_t mdmatime = 0x1c175;
152 
    uint32_t udmatime = 0x5071152;
153 
    uint32_t param = 0;
154 
    ata_dma_flags = 0;
155 
    ata_lba48 = ata_identify_data[83] & BIT(10) ? true : false;
156 
    if (ata_lba48)
157 
        ata_total_sectors = ata_identify_data[100]
158 
                          | (((uint64_t)ata_identify_data[101]) << 16)
159 
                          | (((uint64_t)ata_identify_data[102]) << 32)
160 
                          | (((uint64_t)ata_identify_data[103]) << 48);
161 
    else ata_total_sectors = ata_identify_data[60] | (((uint32_t)ata_identify_data[61]) << 16);
162 
    if (ata_identify_data[53] & BIT(1))
163 
    {
164 
        if (ata_identify_data[64] & BIT(1)) piotime = 0x2072;
165 
        else if (ata_identify_data[64] & BIT(0)) piotime = 0x7083;
166 
    }
167 
    if (ata_identify_data[63] & BIT(2))
168 
    {
169 
        mdmatime = 0x5072;
170 
        param = 0x22;
171 
    }
172 
    else if (ata_identify_data[63] & BIT(1))
173 
    {
174 
        mdmatime = 0x7083;
175 
        param = 0x21;
176 
    }
177 
    if (ata_identify_data[63] & BITRANGE(0, 2))
178 
    {
179 
        ata_dma_flags = BIT(3) | BIT(10);
180 
        param |= 0x20;
181 
    }
182 
    if (ata_identify_data[53] & BIT(2))
183 
    {
184 
        if (ata_identify_data[88] & BIT(4))
185 
        {
186 
            udmatime = 0x2010a52;
187 
            param = 0x44;
188 
        }
189 
        else if (ata_identify_data[88] & BIT(3))
190 
        {
191 
            udmatime = 0x2020a52;
192 
            param = 0x43;
193 
        }
194 
        else if (ata_identify_data[88] & BIT(2))
195 
        {
196 
            udmatime = 0x3030a52;
197 
            param = 0x42;
198 
        }
199 
        else if (ata_identify_data[88] & BIT(1))
200 
        {
201 
            udmatime = 0x3050a52;
202 
            param = 0x41;
203 
        }
204 
        if (ata_identify_data[88] & BITRANGE(0, 4))
205 
        {
206 
            ata_dma_flags = BIT(2) | BIT(3) | BIT(9) | BIT(10);
207 
            param |= 0x40;
208 
        }
209 
    }
210 
    ata_dma = param ? true : false;
317 theseven 211 
    PASS_RC(ata_set_feature(0xef, param), 2, 1);
212 
    if (ata_identify_data[82] & BIT(5)) PASS_RC(ata_set_feature(2, 0), 2, 2);
213 
    if (ata_identify_data[82] & BIT(6)) PASS_RC(ata_set_feature(0x55, 0), 2, 3);
301 theseven 214 
    ATA_PIO_TIME = piotime;
215 
    ATA_MDMA_TIME = mdmatime;
216 
    ATA_UDMA_TIME = udmatime;
217 
    ata_powered = true;
218 
    ata_set_active();
219 
    return 0;
220 
}
221 
 
222 
void ata_power_down()
223 
{
224 
    ata_powered = false;
225 
    ata_wait_for_rdy(1000000);
226 
    ata_write_cbr(&ATA_PIO_DVR, 0);
227 
    ata_write_cbr(&ATA_PIO_CSD, 0xe0);
228 
    ata_wait_for_rdy(1000000);
229 
    sleep(30000);
230 
    ATA_CONTROL = 0;
317 theseven 231 
    while (!(ATA_CONTROL & BIT(1))) yield();
301 theseven 232 
    clockgate_enable(5, false);
233 
    i2c_sendbyte(0, 0xe6, 0x1b, 0);
234 
}
235 
 
236 
int ata_rw_sectors(uint64_t sector, uint32_t count, void* buffer, bool write)
237 
{
238 
    if (sector + count > ata_total_sectors) RET_ERR(0);
239 
    if (!ata_powered) ata_power_up();
240 
    ata_set_active();
241 
    if (ata_dma && write) clean_dcache();
242 
    else if (ata_dma) invalidate_dcache();
243 
    ATA_COMMAND = BIT(1);
244 
    while (count)
245 
    {
317 theseven 246 
        uint32_t cnt = MIN(ata_lba48 ? 8192 : 32, count);
301 theseven 247 
        PASS_RC(ata_wait_for_rdy(100000), 2, 0);
248 
        ata_write_cbr(&ATA_PIO_DVR, 0);
249 
        if (ata_lba48)
250 
        {
251 
            ata_write_cbr(&ATA_PIO_SCR, cnt >> 5);
252 
            ata_write_cbr(&ATA_PIO_SCR, (cnt << 3) & 0xff);
253 
            ata_write_cbr(&ATA_PIO_LHR, (sector >> 37) & 0xff);
254 
            ata_write_cbr(&ATA_PIO_LMR, (sector >> 29) & 0xff);
255 
            ata_write_cbr(&ATA_PIO_LLR, (sector >> 21) & 0xff);
256 
            ata_write_cbr(&ATA_PIO_LHR, (sector >> 13) & 0xff);
257 
            ata_write_cbr(&ATA_PIO_LMR, (sector >> 5) & 0xff);
258 
            ata_write_cbr(&ATA_PIO_LLR, (sector << 3) & 0xff);
259 
            ata_write_cbr(&ATA_PIO_DVR, BIT(6));
260 
            if (write) ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0x35 : 0x39);
261 
            else ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0x25 : 0x29);
262 
        }
263 
        else
264 
        {
265 
            ata_write_cbr(&ATA_PIO_SCR, (cnt << 3) & 0xff);
266 
            ata_write_cbr(&ATA_PIO_LHR, (sector >> 13) & 0xff);
267 
            ata_write_cbr(&ATA_PIO_LMR, (sector >> 5) & 0xff);
268 
            ata_write_cbr(&ATA_PIO_LLR, (sector << 3) & 0xff);
269 
            ata_write_cbr(&ATA_PIO_DVR, BIT(6) | ((sector >> 21) & 0xf));
270 
            if (write) ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0xca : 0x30);
271 
            else ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0xc8 : 0xc4);
272 
        }
273 
        sector += cnt;
274 
        count -= cnt;
275 
        if (ata_dma)
276 
        {
316 theseven 277 
            PASS_RC(ata_wait_for_start_of_transfer(10000000), 2, 1);
301 theseven 278 
            if (write)
279 
            {
280 
                ATA_SBUF_START = buffer;
281 
                ATA_SBUF_SIZE = SECTOR_SIZE * cnt;
282 
                ATA_CFG |= BIT(4);
283 
            }
284 
            else
285 
            {
286 
                ATA_TBUF_START = buffer;
287 
                ATA_TBUF_SIZE = SECTOR_SIZE * cnt;
288 
                ATA_CFG &= ~BIT(4);
289 
            }
290 
            ATA_XFR_NUM = SECTOR_SIZE * cnt - 1;
291 
            ATA_CFG |= ata_dma_flags;
292 
            ATA_CFG &= ~(BIT(7) | BIT(8));
293 
            wakeup_wait(&ata_wakeup, TIMEOUT_NONE);
294 
            ATA_IRQ = BITRANGE(0, 4);
295 
            ATA_IRQ_MASK = BIT(0);
296 
            ATA_COMMAND = BIT(0);
316 theseven 297 
            if (wakeup_wait(&ata_wakeup, 10000000) == THREAD_TIMEOUT)
301 theseven 298 
            {
299 
                ATA_COMMAND = BIT(1);
300 
                ATA_CFG &= ~(BITRANGE(2, 3) | BIT(12));
301 
                RET_ERR(2);
302 
            }
303 
            ATA_COMMAND = BIT(1);
304 
            ATA_CFG &= ~(BITRANGE(2, 3) | BIT(12));
305 
            buffer += SECTOR_SIZE * cnt;
306 
        }
307 
        else
308 
        {
309 
            cnt *= SECTOR_SIZE / 512;
310 
            while (cnt--)
311 
            {
312 
                int i;
316 theseven 313 
                PASS_RC(ata_wait_for_start_of_transfer(10000000), 2, 1);
301 theseven 314 
                if (write)
315 
                    for (i = 0; i < 256; i++)
316 
                        ata_write_cbr(&ATA_PIO_DTR, ((uint16_t*)buffer)[i]);
317 
                else
318 
                    for (i = 0; i < 256; i++)
319 
                        ((uint16_t*)buffer)[i] = ata_read_cbr(&ATA_PIO_DTR);
320 
                buffer += 512;
321 
            }
322 
        }
323 
        PASS_RC(ata_wait_for_end_of_transfer(100000), 2, 3);
324 
    }
325 
    ata_set_active();
326 
    return 0;
327 
}
328 
 
329 
static void ata_thread(void)
330 
{
331 
    while (true)
332 
    {
333 
        mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
334 
        if (TIME_AFTER(USEC_TIMER, ata_last_activity_value + ata_sleep_timeout) && ata_powered)
335 
            ata_power_down();
336 
        mutex_unlock(&ata_mutex);
337 
        sleep(1000000);
338 
    }
339 
}
340 
 
341 
/* API Functions */
342 
int ata_soft_reset()
343 
{
344 
    mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
345 
    if (!ata_powered) ata_power_up();
346 
    ata_set_active();
347 
    ata_write_cbr(&ATA_PIO_DAD, BIT(1) | BIT(2));
348 
    sleep(10);
349 
    ata_write_cbr(&ATA_PIO_DAD, 0);
350 
    PASS_RC_MTX(ata_wait_for_rdy(5000000), 0, 0, &ata_mutex);
351 
    ata_set_active();
352 
    mutex_unlock(&ata_mutex);
353 
}
354 
 
355 
int ata_read_sectors(IF_MD2(int drive,) unsigned long start, int incount,
356 
                     void* inbuf)
357 
{
358 
    mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
316 theseven 359 
    int tries = 3;
301 theseven 360 
    int rc = -1;
361 
    while (--tries && rc)
362 
    {
363 
        rc = ata_rw_sectors(start, incount, inbuf, false);
364 
        if (rc) ata_soft_reset();
365 
    }
366 
    mutex_unlock(&ata_mutex);
367 
    return rc;
368 
}
369 
 
370 
int ata_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
371 
                      const void* outbuf)
372 
{
373 
    mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
316 theseven 374 
    int tries = 3;
301 theseven 375 
    int rc = -1;
376 
    while (--tries && rc)
377 
    {
378 
        rc = ata_rw_sectors(start, count, (void*)((uint32_t)outbuf), true);
379 
        if (rc) ata_soft_reset();
380 
    }
381 
    mutex_unlock(&ata_mutex);
382 
    return rc;
383 
}
384 
 
385 
void ata_spindown(int seconds)
386 
{
387 
    ata_sleep_timeout = seconds * 1000000;
388 
}
389 
 
390 
void ata_sleep(void)
391 
{
392 
    call_storage_idle_notifys(false);
393 
    mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
394 
    ata_power_down();
395 
    mutex_unlock(&ata_mutex);
396 
}
397 
 
398 
void ata_sleepnow(void)
399 
{
400 
    ata_sleep();
401 
}
402 
 
403 
void ata_close(void)
404 
{
405 
    ata_sleep();
406 
}
407 
 
408 
void ata_spin(void)
409 
{
410 
    ata_power_up();
411 
}
412 
 
413 
void ata_get_info(IF_MD2(int drive,) struct storage_info *info)
414 
{
415 
    (*info).sector_size = SECTOR_SIZE;
416 
    (*info).num_sectors = ata_total_sectors;
417 
    (*info).vendor = "Apple";
418 
    (*info).product = "iPod Classic";
419 
    (*info).revision = "1.0";
420 
}
421 
 
422 
long ata_last_disk_activity(void)
423 
{
424 
    return ata_last_activity_value;
425 
}
426 
 
427 
int ata_init(void)
428 
{
429 
    mutex_init(&ata_mutex);
430 
    wakeup_init(&ata_wakeup);
431 
    PCON(7) = 0x44444444;
432 
    PCON(8) = 0x44444444;
433 
    PCON(9) = 0x44444444;
434 
    PCON(10) = (PCON(10) & ~0xffff) | 0x4444;
435 
    ata_powered = false;
436 
    ata_total_sectors = 0;
437 
    thread_create("ATA idle monitor", ata_thread, ata_stack,
438 
                  sizeof(ata_stack), USER_THREAD, 1, true);
439 
    return 0;
440 
}
441 
 
442 
#ifdef CONFIG_STORAGE_MULTI
443 
int ata_num_drives(int first_drive)
444 
{
445 
    /* We don't care which logical drive number(s) we have been assigned */
446 
    (void)first_drive;
447 
 
448 
    return 1;
449 
}
450 
#endif
451 
 
452 
void INT_ATA()
453 
{
454 
    uint32_t ata_irq = ATA_IRQ;
455 
    ATA_IRQ = ata_irq;
456 
    if (ata_irq & ATA_IRQ_MASK) wakeup_signal(&ata_wakeup);
457 
    ATA_IRQ_MASK = 0;
458 
}