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725 theseven 1 
@
2 
@
3 
@    emCORE Loader for iPod Nano 4G
4 
@
5 
@    Copyright 2011 TheSeven, Farthen
6 
@
7 
@
8 
@    This file is part of emCORE.
9 
@
10 
@    emCORE is free software: you can redistribute it and/or
11 
@    modify it under the terms of the GNU General Public License as
12 
@    published by the Free Software Foundation, either version 2 of the
13 
@    License, or (at your option) any later version.
14 
@
15 
@    emCORE is distributed in the hope that it will be useful,
16 
@    but WITHOUT ANY WARRANTY; without even the implied warranty of
17 
@    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
18 
@    See the GNU General Public License for more details.
19 
@
20 
@    You should have received a copy of the GNU General Public License along
21 
@    with emCORE.  If not, see <http://www.gnu.org/licenses/>.
22 
@
23 
@
24 
 
25 
.global _start
26 
_start:
27 
	msr	cpsr_c, #0xd3
28 
	mrc	p15, 0, r0,c1,c0
29 
	bic	r0, r0, #1
30 
	mcr	p15, 0, r0,c1,c0 @ disable mmu
31 
 
32 
	mov	lr, #0
33 
	mcr	p15, 0, lr,c7,c14,0 @ clean & invalidate data cache
34 
	mcr	p15, 0, lr,c7,c10,4 @ drain write buffer
35 
	mcr	p15, 0, lr,c7,c5    @ invalidate instruction cache
726 theseven 36 
	mcr	p15, 0, lr,c7,c5,4  @ flush prefetch buffer
725 theseven 37 
	mcr	p15, 0, lr,c8,c7    @ invalidate all unlocked entries in the TLB
38 
	mcr	p15, 0, lr,c13,c0,0 @ disable context id register
39 
 
726 theseven 40 
	adr	sp, values1
41 
 
42 
.macro block0_constpool    @ Block 0 (MMU) register map:
725 theseven 43 
                           @ R0: Unused
44 
                           @ R1: Unused
45 
                           @ R2: Unused
46 
                           @ R3: Scratchpad
726 theseven 47 
                           @ R4: Unused
48 
                           @ R5: Unused
49 
                           @ R6: Unused
50 
                           @ R7: Unused
51 
                           @ R8: Unused
52 
                           @ R9: Unused
53 
	.word	0x0005187D @ R10: CP15r1
725 theseven 54 
	.word	0x2202C000 @ R11: First level page table
55 
	.word	0x00000C1E @ R12: Default segment flags
56 
                           @ R13: Constant pool pointer
57 
.endm                      @ R14: 0
58 
 
59 
	ldmia	sp!, {r10-r12}
60 
	mcr	p15, 0, r11,c2,c0 @ set first level translation table
61 
	mov	r3, #-1
62 
	mcr	p15, 0, r3,c3,c0 @ disable domain access control                  @ R3: Unused
726 theseven 63 
	orr	r0, r12, #0x22000000
64 
	str	r0, [r11], #4
65 
	add	r12, r12, #0x00100000
725 theseven 66 
mmuloop:
67 
	str	r12, [r11], #4
68 
	add	r12, r12, #0x00100000
69 
	cmp	r12, #0x38000000
70 
	biccs	r12, r12, #0xc
71 
	tst	r12, #0x40000000
72 
	beq	mmuloop
726 theseven 73 
                                                                                  @ R11: Unused
74 
                                                                                  @ R12: Unused
725 theseven 75 
	mcr	p15, 0, r10,c1,c0                                                 @ R10: Unused
76 
 
726 theseven 77 
 
78 
.macro block1_constpool    @ Block 1 (SYSCON) register map:
725 theseven 79 
	.word	0x000327E5 @ R0: PWRCON(0)
80 
	.word	0xFE2BED6D @ R1: PWRCON(1)
81 
	.word	0x00DCF779 @ R2: PWRCON(4)
82 
	.word	0x003E3E00 @ R3
83 
	.word	0x06008501 @ R4
84 
	.word	0x00009DBC @ R5
85 
	.word	0x00404040 @ R6
86 
	.word	0x40001000 @ R7
87 
	.word	0x80008000 @ R8
88 
	.word	0x38501000 @ R9
89 
	.word	0xE02BED4D @ R10: PWRCON(1) during timer setup
90 
	.word	0x001CF700 @ R11: PWRCON(4) during timer setup
91 
	.word	0x3C500000 @ R12: SYSCON base address
92 
                           @ R13: Constant pool pointer
93 
.endm                      @ R14: 0
94 
 
95 
	ldmia	sp!, {r0-r12}
726 theseven 96 
	str	r0, [r12,#0x48]  @ PWRCON0 ...                                    @ R0: Scratchpad
725 theseven 97 
	str	r1, [r12,#0x4c]
98 
	mov	r0, #0x73
99 
	str	r0, [r12,#0x58]
100 
	mov	r0, #0xff
101 
	str	r0, [r12,#0x68]
102 
	str	r2, [r12,#0x6c]  @ ... PWRCON4
103 
	str	lr, [r12]
104 
sysconwait1:
105 
	ldr	r0, [r12]
106 
	tst	r0, #0xf
107 
	bne	sysconwait1      @ while ([SYSCON] & 0xf)
108 
 
109 
	str	lr, [r12,#0x04]
110 
sysconwait2:
111 
	ldr	r0, [r12,#0x04]
112 
	tst	r0, r3
113 
	bne	sysconwait2      @ while ([SYSCON+4] & 0x003E3E00)
114 
 
115 
	mov	r0, #0x7
116 
	str	r0, [r12,#0x44]
117 
	str	lr, [r12,#0x44]
118 
	str	lr, [r12,#0x3c]
726 theseven 119 
	str	r4, [r12,#0x20]                                                   @ R4: Scratchpad
725 theseven 120 
	str	r5, [r12,#0x30]
121 
	mov	r5, #1                                                            @ R5: 1
122 
	str	r5, [r12,#0x44]
123 
	orr	r4, r0, #0x10000
124 
	str	r4, [r12,#0x44]
125 
sysconwait3:
126 
	ldr	r4, [r12,#0x40]
127 
	tst	r4, #0x1
128 
	beq	sysconwait3      @ while (!([SYSCON+0x40] & 1))
129 
 
726 theseven 130 
	str	r6, [r12,#0x04]                                                   @ R6: Unused
725 theseven 131 
	add	r3, r3, #0x3e                                                     @ R3: 0x003E3E3E
132 
sysconwait4:
133 
	ldr	r4, [r12,#0x04]
726 theseven 134 
	tst	r4, r3                                                            @ R3: Unused
725 theseven 135 
	bne	sysconwait4
136 
 
726 theseven 137 
	str	r7, [r12]                                                         @ R7: Unused
725 theseven 138 
sysconwait5:
139 
	ldr	r2, [r12]
140 
	tst	r4, #0xf
141 
	bne	sysconwait5
142 
 
143 
	str	r8, [r12,#0x08]
726 theseven 144 
	orr	r4, r8, r8,lsr#1                                                  @ R8: Unused
725 theseven 145 
	str	r4, [r12,#0x0c]
146 
	mov	r4, #0xc000
147 
	str	r4, [r12,#0x10]
148 
	mov	r4, #0x8000
149 
	str	r4, [r12,#0x14]
150 
	str	r4, [r12,#0x70]
151 
	mov	r4, #2
152 
	str	r4, [r9]                                                          @ R9: Unused
153 
	mov	r0, #0x10                                                         @ R5: 0x10
154 
 
726 theseven 155 
                           @ Block 2 (TIMER) register map:
156 
                           @ R0: 1
157 
                           @ R1: PWRCON(1)
158 
                           @ R2: PWRCON(4)
159 
                           @ R3: Scratchpad
160 
                           @ R4: Scratchpad
161 
                           @ R5: 0x10
162 
                           @ R6: Unused
163 
                           @ R7: Unused
164 
                           @ R8: Unused
165 
                           @ R9: Unused
166 
                           @ R10: PWRCON(1) during timer setup
167 
                           @ R11: PWRCON(4) during timer setup
168 
                           @ R12: SYSCON base address
725 theseven 169 
                           @ R13: Constant pool pointer
170 
                           @ R14: 0
171 
 
172 
	str	r10, [r12,#0x4c]     @ PWRCON(1) for timer setup                  @ R10: Unused
173 
	mov	r4, #0x13
726 theseven 174 
	str	r4, [r12,#0x58]             @ PWRCON(2) for timer setup
725 theseven 175 
	str	r11, [r12,#0x6c]     @ PWRCON(4) for timer setup                  @ R11: Unused
176 
	orr     r11, r12, #0x00200000                                             @ R11: TIMER base address
177 
	str	r0, [r11,#0x4]       @ TACMD = 0x10
178 
	str	r0, [r11,#0x24]      @ TBCMD = 0x10
179 
	str	r0, [r11,#0x44]      @ TCCMD = 0x10
180 
	str	r0, [r11,#0x64]      @ TDCMD = 0x10
181 
	mov	r3, #0x40
182 
	str	r3, [r11,#0xa0]      @ TECON = 0x40
183 
	mov	r3, #0xb
184 
	str	r3, [r11,#0xb0]      @ TEPRE = 0xb
185 
	mov	r4, #-1                                                           @ R4: -1
186 
	str	r4, [r11,#0xa8]      @ TEDATA0 = 0xFFFFFFFF
187 
	mov	r3, #0x3
188 
	str	r3, [r11,#0xa4]      @ TECMD = 0x3
189 
	str	r0, [r11,#0xc4]      @ TFCMD = 0x10
190 
	str	r0, [r11,#0xe4]      @ TGCMD = 0x10
191 
	str	r0, [r11,#0x104]     @ THCMD = 0x10
192 
	str	r4, [r11,#0x118]     @ THCMD = 0xFFFFFFFF
193 
	str	r1, [r12,#0x4c]      @ PWRCON(1)                                  @ R1: Unused
194 
	mov	r3, #0x73
195 
	str	r3, [r12,#0x58]      @ PWRCON(2)
726 theseven 196 
	str	r2, [r12,#0x6c]      @ PWRCON(4)                                  @ R2: Unused
725 theseven 197 
	orr	r10, r11, #0x00800000                                             @ R10: GPIO base address
198 
 
726 theseven 199 
                           @ Block 3 (GPIO) register map:
200 
                           @ R0: Unused
201 
                           @ R1: Unused
202 
                           @ R2: Unused
203 
                           @ R3: Scratchpad
204 
                           @ R4: -1
205 
                           @ R5: 1
206 
                           @ R6: Unused
207 
                           @ R7: Unused
208 
                           @ R8: Unused
209 
                           @ R9: Unused
210 
                           @ R10: GPIO base address
211 
                           @ R11: TIMER base address
212 
                           @ R12: SYSCON base address
725 theseven 213 
                           @ R13: Constant pool pointer
214 
                           @ R14: 0
215 
 
216 
.macro gpio_initdata
217 
	.word	0x3202EEEE @ PCON0
218 
	.word	0xE0EE2253 @ PCON1
219 
	.word	0x2223EEEE @ PCON2
220 
	.word	0x33333332 @ PCON3
221 
	.word	0xFF333E33 @ PCON4
222 
	.word	0xE0FEE200 @ PCON5
223 
	.word	0x2222222E @ PCON6
224 
	.word	0x22222222 @ PCON7
225 
	.word	0xEEEEEEE2 @ PCON8
226 
	.word	0xEEE0EEEE @ PCON9
227 
	.word	0x2EEEEEEE @ PCONA
228 
	.word	0xEEEE0222 @ PCONB
229 
	.word	0xEEEEE00E @ PCONC
230 
	.word	0xEEEEEEEE @ PCOND
231 
	.word	0xEEEEEEEE @ PCONE
232 
.endm
233 
 
234 
	ldr	r3, [sp], #0x4
726 theseven 235 
	str	r3, [r10], #0xc                                                   @ R10: PCONx iterator
725 theseven 236 
	mov	r3, #0x20
237 
	str	r3, [r10], #0x4     @ PCON0 + 0xc = 0x20
238 
	mov	r3, #0x40
239 
	str	r3, [r10], #0x10    @ PCON0 + 0x10 = 0x40
240 
	add	r9, r10, #0x1a0                                                   @ R9: Iterator limit
241 
gpioloop1:
242 
	ldr	r3, [sp], #0x4
243 
	str	r3, [r10], #0xc
244 
	str	lr, [r10], #0x4     @ PCON + 0xc = 0
245 
	str	lr, [r10], #0x10    @ PCON + 0x10 = 0
246 
	cmp	r10, r9
247 
	bls	gpioloop1
726 theseven 248 
                                                                                  @ R10: 0x3CF001E0
725 theseven 249 
	ldr	r3, [r10,#0x1a8]
250 
	bic	r3, r3, #2
251 
	orr	r3, r3, #1
252 
	str	r3, [r10,#0x1a8]
253 
	sub	r8, r11, #0x00300000                                              @ R8: 0x39700000 (iterator)
254 
	mov	r9, #6                                                            @ R9: Iterations remaining
255 
gpioloop2:
256 
	str	r14, [r8,#0x80]
257 
	str	r4, [r8,#0xa0]
258 
	str	r14, [r8,#0xc0]
259 
	str	r14, [r8,#0xe0]
260 
	add	r8, r8, #4
261 
	subs	r9, r9, #1
262 
	bne	gpioloop2
726 theseven 263 
                                                                                  @ R9: 0
264 
	ldr	r8, [r10,#-0x180]                                                 @ R8: PCON3 backup
725 theseven 265 
	and	r3, r8, #0xff
266 
	str	r3, [r10,#-0x180]   @ *PCON3 &= 0xff
726 theseven 267 
	mov	r0, #0x3e8                                                        @ R0: Scratchpad
268 
	bl	udelay                                                            @ R14: Return address
725 theseven 269 
	ldr	r3, [r10,#-0x17c]
270 
	and	r3, r3, #0xfc
271 
	mov	r6, r3, lsr #0x2                                                  @ R6: Data for first PMU access
272 
	str	r8, [r10,#-0x180]
273 
	bic	r10, r11, #0x00100000                                             @ R10: I2C base address
274 
 
726 theseven 275 
                           @ Block 4 (I2C) register map:
276 
                           @ R0: Scratchpad
277 
                           @ R1: Scratchpad
278 
                           @ R2: Unused
279 
                           @ R3: Unused
280 
                           @ R4: -1
281 
                           @ R5: 1
282 
                           @ R6: Data for first PMU access
283 
                           @ R7: Unused
284 
                           @ R8: Unused
285 
                           @ R9: 0
286 
                           @ R10: I2C base address
287 
                           @ R11: TIMER base address
288 
                           @ R12: SYSCON base address
725 theseven 289 
                           @ R13: Constant pool pointer
290 
                           @ R14: Return address / Scratchpad
291 
 
292 
	bl	i2cwaitrdy
293 
	mov	r1, #0x40
294 
	str	r1, [r10,#0x08]
295 
	bl	i2cwaitrdy
296 
	str	r5, [r10,#0x14]
297 
	bl	i2cwaitrdy
298 
	str	r9, [r10,#0x18]
299 
	bl	i2cwaitrdy
300 
	mov	r0, #0x80
301 
	str	r0, [r10,#0x04]
302 
	bl	i2cwaitrdy
303 
	str	r9, [r10]
304 
	bl	i2cwaitrdy
305 
	str	r9, [r10,#0x04]
306 
	bl	i2cwaitrdy
307 
	str	r1, [r10,#0x0c]
308 
	bl	i2cwaitrdy
309 
	orr	r0, r5, #0x180
310 
	str	r0, [r10]
311 
	bl	i2cwaitrdy
312 
	mov	r0, #0x10
313 
	str	r0, [r10,#0x04]
314 
	bl	i2cwaitrdy
315 
 
726 theseven 316 
                           @ Block 5 (PMU) register map:
317 
                           @ R0: Address / Scratchpad (trashed by pmubatch)
318 
                           @ R1: Data / Scratchpad (trashed by pmubatch)
319 
                           @ R2: Scratchpad (set to 0xb7 by pmu accesses)
320 
                           @ R3: Scratchpad (set to 0x10 by pmu accesses)
321 
                           @ R4: Scratchpad (trashed by pmu accesses)
322 
                           @ R5: 1
323 
                           @ R6: Data for first PMU access
324 
                           @ R7: Scratchpad (trashed by pmubatch)
325 
                           @ R8: Used to store warmboot flag
326 
                           @ R9: 0 / pmubatch transfer count (reset to 0 by pmubatch)
327 
                           @ R10: I2C base address
328 
                           @ R11: TIMER base address
329 
                           @ R12: SYSCON base address
725 theseven 330 
                           @ R13: Constant pool / pmubatch data pointer
331 
                           @ R14: Return address / Scratchpad
332 
 
333 
	mov	r0, #0x7f
334 
	mov	r1, r6
335 
	bl	pmuwrite
336 
	mov	r0, #0x02
337 
	bl	pmuread
338 
	ands	r8, r1, #0x80                                                     @ R8: Warmboot flag
339 
	beq	pmu_coldboot
340 
	mov	r1, #0x80
341 
	bl	pmuwrite
342 
pmu_coldboot:
343 
.macro pmu_batch_1
344 
pmu_batch_1_begin:
345 
	.byte	0x14, 0x13
346 
	.byte	0x15, 0x0d
347 
	.byte	0x0b, 0x22
348 
pmu_batch_1_end:
349 
.endm
350 
	mov	r9, #(pmu_batch_1_end - pmu_batch_1_begin) / 2
351 
	bl	pmubatch
726 theseven 352 
	tst	r6, #1                                                            @ R6: Unused
725 theseven 353 
	beq	pmu_skip
354 
	mov	r0, #0x0d
355 
	bl	pmuread
356 
	and	r1, r1, #0xdf
357 
	bl	pmuwrite
358 
pmu_skip:
359 
.macro pmu_batch_2
360 
pmu_batch_2_begin:
361 
	.byte	0x1f, 0x14
362 
	.byte	0x1a, 0xb2
363 
	.byte	0x1a, 0xb2
364 
	.byte	0x19, 0x14
365 
	.byte	0x21, 0x06
366 
	.byte	0x1d, 0x12
367 
pmu_batch_2_end:
368 
.endm
369 
	mov	r9, #(pmu_batch_2_end - pmu_batch_2_begin) / 2
370 
	bl	pmubatch
371 
	mov	r0, #0x10
372 
	bl	pmuread
373 
	bic	r1, r1, #0x80
374 
	orr	r1, r1, #0x60
726 theseven 375 
	bl	pmuwrite
725 theseven 376 
.macro pmu_batch_3
377 
pmu_batch_3_begin:
378 
	.byte	0x44, 0x72
379 
pmu_batch_3_end:
380 
.endm
381 
	mov	r9, #(pmu_batch_3_end - pmu_batch_3_begin) / 2
382 
	bl	pmubatch
383 
	mov	r0, #0x40
384 
	bl	pmuread
385 
	orr	r1, r1, #0x40
386 
	bl	pmuwrite
387 
	mov	r0, #0x33
388 
	bl	pmuread
389 
	and	r1, r1, #0x03
390 
	orr	r1, r1, #0x50
391 
	bl	pmuwrite
392 
	mov	r0, #0x34
393 
	bl	pmuread
394 
	and	r1, r1, #0x80
395 
	orr	r1, r1, #0x54
396 
	bl	pmuwrite
397 
.macro pmu_batch_4
398 
pmu_batch_4_begin:
399 
	.byte	0x22, 0x00
400 
	.byte	0x07, 0x50
401 
	.byte	0x08, 0xfe
402 
	.byte	0x09, 0x2b
403 
	.byte	0x01, 0xff
404 
	.byte	0x02, 0xff
405 
	.byte	0x03, 0xff
406 
pmu_batch_4_end:
407 
.endm
408 
	mov	r9, #(pmu_batch_4_end - pmu_batch_4_begin) / 2
409 
	bl	pmubatch
410 
	cmp	r8, #0
411 
	bne	pmu_warmboot
412 
	mov	r0, #0x30
413 
	mov	r1, #0x64
414 
	bl	pmuwrite
415 
pmu_warmboot:
416 
	mov	r0, #0x31
417 
	bl	pmuread
418 
	bic	r1, r1, #0x01
419 
	bl	pmuwrite
420 
.macro pmu_batch_5
421 
pmu_batch_5_begin:
422 
	.byte	0x0a, 0x70
423 
	.byte	0x13, 0x02
424 
pmu_batch_5_end:
425 
.endm
426 
	mov	r9, #(pmu_batch_5_end - pmu_batch_5_begin) / 2
427 
	bl	pmubatch
428 
 
726 theseven 429 
	orr	lr, r11, #0x00800000                                              @ R14: GPIO base address
725 theseven 430 
	str	r9, [lr,#0x384]
726 theseven 431 
	orr	lr, r11, #0x01000000                                              @ R14: MIU base address
725 theseven 432 
	str	r5, [lr]
433 
	ldrh	r0, [sp], #2
434 
	str	r0, [lr,#0x100]
435 
	mov	r0, #0xff
436 
	str	r0, [lr,#0x11c]
437 
	str	r0, [lr,#0x120]
438 
 
726 theseven 439 
.macro block6_constpool           @ Block 6 (SDRAM) register map:
725 theseven 440 
	.hword	0x1030
441 
	.word	0x008AAC25 @ R0
442 
	.word	0x050D67E5 @ R1
443 
	.word	0x0002000B @ R2
444 
	.word	0x0003B3B2 @ R3
445 
	.word	0xFF53B3B0 @ R4
446 
	.word	0x00008040 @ R5
447 
	.word	0x8000100F @ R6: For LCD init at end of block
749 theseven 448 
	.word	0x41000c20 @ R7: For LCD init at end of block
726 theseven 449 
                           @ R8: Warmboot flag
450 
                           @ R9: 0
451 
                           @ R10: I2C base address
452 
                           @ R11: TIMER base address
453 
                           @ R12: SYSCON base address
725 theseven 454 
                           @ R13: Constant pool pointer
455 
.endm                      @ R14: MIU base address
456 
 
457 
	ldmia	sp!, {r0-r7}
726 theseven 458 
	str	r0, [lr,#0x114]                                                   @ R0: Unused
459 
	str	r1, [lr,#0x124]                                                   @ R1: Unused
460 
	mov	r0, #8                                                            @ R0: Scratchpad
725 theseven 461 
	str	r0, [lr,#0x118]
462 
	str	r2, [lr,#0x108]
463 
	mov	r0, #4
464 
	str	r0, [lr,#0x148]
465 
	str	r9, [lr,#0x14c]
466 
	str	r3, [lr,#0x140]
467 
miu_wait1:
468 
	ldr	r0, [lr,#0x140]
469 
	tst	r0, #2
470 
	beq	miu_wait1
726 theseven 471 
	add	r0, r3, #1                                                        @ R3: Unused
725 theseven 472 
	str	r0, [lr,#0x140]
473 
miu_wait2:
474 
	ldr	r0, [lr,#0x144]
475 
	mvn	r0, r0
476 
	tst	r0, #3
477 
	bne	miu_wait2
726 theseven 478 
	ldr	r1, [lr,#0x144]                                                   @ R1: Scratchpad
725 theseven 479 
	mov	r0, #0x0ff00000
726 theseven 480 
	and	r0, r0, r1, lsl#2
481 
	add	r0, r0, r4                                                        @ R4: Unused
725 theseven 482 
	str	r0, [lr,#0x140]
483 
	mov	r0, #0x10
484 
	str	r0, [lr,#0x150]
726 theseven 485 
	cmp	r8, #0                                                            @ R8: Unused
725 theseven 486 
	sub	r8, r10, #0x04300000                                              @ R8: LCD base address
487 
	str	r6, [r12,#0x08]                                                   @ R6: Unused
488 
	str	r7, [r8]                                                          @ R7: Unused
489 
	mov	r0, #0x11
490 
	str	r0, [r8,#0x20]
726 theseven 491 
	mov	r3, #0x33                                                         @ R3: 0x33
725 theseven 492 
	beq	miu_coldboot
493 
	str	r0, [lr,#0x104]
494 
	b	miu_common
495 
miu_coldboot:
496 
	str	r3, [lr,#0x104]
497 
	orr	r0, r3, #0x200
498 
	str	r0, [lr,#0x104]
499 
miu_wait3:
500 
	ldr	r0, [lr,#0x104]
501 
	tst	r0, #0x110000
502 
	bne	miu_wait3
503 
	str	r3, [lr,#0x104]
504 
	str	r3, [lr,#0x104]
505 
	str	r3, [lr,#0x104]
506 
	orr	r1, r3, #0x300
507 
	str	r1, [lr,#0x104]
508 
miu_wait4:
509 
	ldr	r0, [lr,#0x104]
510 
	tst	r0, #0x110000
511 
	bne	miu_wait4
512 
	str	r3, [lr,#0x104]
513 
	str	r3, [lr,#0x104]
514 
	str	r3, [lr,#0x104]
515 
	str	r1, [lr,#0x104]
516 
miu_wait5:
517 
	ldr	r0, [lr,#0x104]
518 
	tst	r0, #0x110000
519 
	bne	miu_wait5
520 
	str	r3, [lr,#0x104]
521 
	str	r3, [lr,#0x104]
522 
	str	r3, [lr,#0x104]
523 
	str	r3, [lr,#0x110]
726 theseven 524 
	orr	r0, r3, #0x100
525 
	str	r0, [lr,#0x104]
725 theseven 526 
miu_wait6:
527 
	ldr	r0, [lr,#0x104]
528 
	tst	r0, #0x110000
529 
	bne	miu_wait6
530 
	str	r3, [lr,#0x104]
531 
	str	r3, [lr,#0x104]
532 
	str	r3, [lr,#0x104]
726 theseven 533 
	str	r5, [lr,#0x110]                                                   @ R5: Unused
725 theseven 534 
	str	r1, [lr,#0x104]
535 
miu_wait7:
536 
	ldr	r0, [lr,#0x104]
537 
	tst	r0, #0x110000
538 
	bne	miu_wait7
539 
	str	r3, [lr,#0x104]
540 
	str	r3, [lr,#0x104]
541 
miu_common:
726 theseven 542 
	str	r3, [lr,#0x104]                                                   @ R3: Unused
725 theseven 543 
	mov	r0, #0x40
544 
	str	r0, [lr,#0x10c]
545 
	ldr	r0, [lr,#0x100]
546 
	orr	r0, r0, #0x9100000
547 
	str	r0, [lr,#0x100]
548 
	mov	r0, #0x19
549 
	str	r0, [lr,#0x11c]
550 
	mov	r0, #1
551 
	str	r0, [lr,#0x120]
726 theseven 552 
	orr	r1, r2, #0x1000                                                   @ R2: Unused
725 theseven 553 
	str	r1, [lr,#0x108]
554 
	str	r0, [lr,#0x08]
555 
	mov	r1, #0x3e000000
556 
	mov	r0, #0x1f
557 
	str	r0, [r1,#0x08]
558 
 
559 
                           @ Block 7 (LCD) register map:
726 theseven 560 
                           @ R0: Cmd/Data to be written / Scratchpad
725 theseven 561 
                           @ R1: Scratchpad
562 
                           @ R2: Scratchpad
563 
                           @ R3: Scratchpad
564 
                           @ R4: Scratchpad
565 
                           @ R5: Scratchpad
566 
                           @ R6: Unused
567 
                           @ R7: Unused
726 theseven 568 
                           @ R8: LCD base address
569 
                           @ R9: 0
570 
                           @ R10: I2C base address
571 
                           @ R11: TIMER base address
572 
                           @ R12: SYSCON base address
725 theseven 573 
                           @ R13: LCD init script pointer / Scratchpad
574 
                           @ R14: Return address / Scratchpad
575 
 
576 
.macro lcd_sequences
577 
lcd_sequences_begin:
578 
	.word	lcd_sequence_c4 - lcd_sequences_begin
579 
	.word	lcd_sequence_d5 - lcd_sequences_begin
580 
	.word	lcd_sequence_e6 - lcd_sequences_begin
581 
	.word	lcd_sequence_b3 - lcd_sequences_begin
582 
lcd_sequence_b3:
583 
	.byte	0x01, 0x11
584 
	.byte	0xf8
585 
	.byte	0x02, 0xfe, 0x00
586 
	.byte	0x02, 0xef, 0x80
587 
	.byte	0x02, 0xc0, 0x0c
588 
	.byte	0x02, 0xc1, 0x03
589 
	.byte	0x03, 0xc2, 0x12, 0x00
590 
	.byte	0x03, 0xc3, 0x12, 0x00
591 
	.byte	0x03, 0xc4, 0x12, 0x00
592 
	.byte	0x03, 0xc5, 0x3a, 0x3e
593 
	.byte	0x03, 0xb1, 0x6a, 0x15
594 
	.byte	0x03, 0xb2, 0x5f, 0x3f
595 
	.byte	0x03, 0xb3, 0x5f, 0x3f
596 
	.byte	0x02, 0xb4, 0x02
597 
	.byte	0x03, 0xb6, 0x12, 0x02
598 
	.byte	0x02, 0x35, 0x00
599 
	.byte	0x02, 0x26, 0x10
600 
	.byte	0x0c, 0xe0, 0x0f, 0x42, 0x24, 0x01, 0x00, 0x02, 0xa6, 0x98, 0x05, 0x04, 0x15
601 
	.byte	0x0c, 0xe1, 0x00, 0x21, 0x44, 0x02, 0x0f, 0x05, 0x89, 0x6a, 0x02, 0x15, 0x04
602 
	.byte	0x0c, 0xe2, 0x7e, 0x04, 0x43, 0x40, 0x00, 0x02, 0x13, 0x00, 0x00, 0x01, 0x0b
603 
	.byte	0x0c, 0xe3, 0x40, 0x40, 0x03, 0x74, 0x0e, 0x00, 0x00, 0x31, 0x02, 0x0b, 0x01
604 
	.byte	0x0c, 0xe4, 0x5a, 0x43, 0x67, 0x56, 0x00, 0x02, 0x67, 0x72, 0x00, 0x05, 0x12
726 theseven 605 
	.byte	0x0c, 0xe5, 0x50, 0x66, 0x47, 0x53, 0x0a, 0x00, 0x27, 0x76, 0x02, 0x12, 0x05
725 theseven 606 
	.byte	0x02, 0x3a, 0x06
607 
	.byte	0x01, 0x13
608 
	.byte	0x01, 0x29
609 
	.byte	0x80
610 
lcd_sequence_c4:
611 
	.byte	0x01, 0x01
612 
	.byte	0x85
613 
	.byte	0x02, 0xc0, 0x00
614 
	.byte	0x02, 0xc1, 0x03
615 
	.byte	0x02, 0xc2, 0x34
616 
	.byte	0x03, 0xc3, 0x72, 0x03
617 
	.byte	0x03, 0xc4, 0x73, 0x03
618 
	.byte	0x03, 0xc5, 0x3c, 0x3c
619 
	.byte	0x02, 0xfe, 0x00
726 theseven 620 
	.byte	0x03, 0xb1, 0x6a, 0x15
725 theseven 621 
	.byte	0x03, 0xb2, 0x6a, 0x15
622 
	.byte	0x03, 0xb3, 0x6a, 0x15
623 
	.byte	0x02, 0xb4, 0x02
624 
	.byte	0x03, 0xb6, 0x12, 0x02
625 
	.byte	0x02, 0x35, 0x00
626 
	.byte	0x02, 0x26, 0x10
627 
	.byte	0x0c, 0xe0, 0x77, 0x52, 0x76, 0x53, 0x03, 0x03, 0x57, 0x42, 0x10, 0x18, 0x09
628 
	.byte	0x0c, 0xe1, 0x0d, 0x00, 0x23, 0x66, 0x0f, 0x15, 0x4d, 0x85, 0x08, 0x02, 0x10
629 
	.byte	0x0c, 0xe2, 0x39, 0x60, 0x77, 0x05, 0x03, 0x07, 0x96, 0x64, 0x0d, 0x1a, 0x0a
630 
	.byte	0x0c, 0xe3, 0x3f, 0x10, 0x16, 0x44, 0x0e, 0x04, 0x6c, 0x44, 0x04, 0x03, 0x0b
631 
	.byte	0x0c, 0xe4, 0x00, 0x61, 0x77, 0x04, 0x02, 0x04, 0x72, 0x32, 0x09, 0x19, 0x06
632 
	.byte	0x0c, 0xe5, 0x4f, 0x42, 0x27, 0x67, 0x0f, 0x02, 0x26, 0x33, 0x01, 0x03, 0x09
633 
	.byte	0x02, 0x36, 0x00
634 
	.byte	0x01, 0x11
635 
	.byte	0x01, 0x29
636 
	.byte	0x80
637 
lcd_sequence_d5:
726 theseven 638 
.byte 0x01, 0x01, 0x85, 0x01, 0x11, 0x01, 0x29, 0x80
725 theseven 639 
	.byte	0x02, 0xfe, 0x00
640 
	.byte	0x02, 0xc0, 0x01
641 
	.byte	0x02, 0xc1, 0x01
642 
	.byte	0x03, 0xc2, 0x03, 0x00
643 
	.byte	0x03, 0xc3, 0x01, 0x00
644 
	.byte	0x03, 0xc4, 0x03, 0x00
645 
	.byte	0x03, 0xc5, 0x34, 0x34
646 
	.byte	0x02, 0xc7, 0x00
647 
	.byte	0x03, 0xb1, 0x6d, 0x15
648 
	.byte	0x03, 0xb2, 0x6d, 0x15
649 
	.byte	0x03, 0xb3, 0x6d, 0x15
650 
	.byte	0x02, 0xb4, 0x03
651 
	.byte	0x03, 0xb6, 0x11, 0x02
652 
	.byte	0x02, 0x35, 0x00
653 
	.byte	0x02, 0x26, 0x10
654 
	.byte	0x0c, 0xe0, 0x23, 0x42, 0x20, 0x42, 0x0e, 0x01, 0xf5, 0xeb, 0x1e, 0x05, 0x18
655 
	.byte	0x0c, 0xe1, 0x5f, 0x22, 0x36, 0x21, 0x03, 0x1e, 0xfe, 0x7b, 0x02, 0x07, 0x18
656 
	.byte	0x0c, 0xe2, 0x5f, 0x34, 0x53, 0x77, 0x0a, 0x00, 0x70, 0xf4, 0x14, 0x06, 0x0f
657 
	.byte	0x0c, 0xe3, 0x0f, 0x23, 0x31, 0x54, 0x0f, 0x0b, 0x8e, 0x08, 0x00, 0x05, 0x15
658 
	.byte	0x0c, 0xe4, 0x5f, 0x33, 0x42, 0x14, 0x0e, 0x04, 0xa6, 0xf7, 0x0e, 0x00, 0x14
659 
	.byte	0x0c, 0xe5, 0x0c, 0x43, 0x44, 0x44, 0x0d, 0x0d, 0x7f, 0x39, 0x03, 0x02, 0x10
660 
	.byte	0x02, 0x3a, 0x66
661 
	.byte	0x02, 0x36, 0x00
662 
	.byte	0x01, 0x11
663 
	.byte	0x01, 0x29
664 
	.byte	0x80
665 
lcd_sequence_e6:
726 theseven 666 
.byte 0x01, 0x11, 0xf8, 0x01, 0x13, 0x01, 0x29, 0x80
725 theseven 667 
	.byte	0x01, 0x11
668 
	.byte	0xf8
669 
	.byte	0x02, 0xfe, 0x00
670 
	.byte	0x02, 0xef, 0x80
671 
	.byte	0x02, 0xc0, 0x13
672 
	.byte	0x02, 0xc1, 0x03
673 
	.byte	0x03, 0xc2, 0x12, 0x00
674 
	.byte	0x03, 0xc3, 0x12, 0x00
675 
	.byte	0x03, 0xc4, 0x12, 0x00
676 
	.byte	0x03, 0xc5, 0x2a, 0x3c
677 
	.byte	0x03, 0xb1, 0x6a, 0x15
678 
	.byte	0x03, 0xb2, 0x5f, 0x3f
679 
	.byte	0x03, 0xb3, 0x5f, 0x3f
680 
	.byte	0x02, 0xb4, 0x02
681 
	.byte	0x03, 0xb6, 0x12, 0x02
682 
	.byte	0x02, 0x35, 0x00
683 
	.byte	0x02, 0x26, 0x10
684 
	.byte	0x0c, 0xe0, 0x0f, 0x53, 0x45, 0x07, 0x00, 0x00, 0xb9, 0xf6, 0x08, 0x04, 0x18
685 
	.byte	0x0c, 0xe1, 0x00, 0x47, 0x55, 0x03, 0x0f, 0x08, 0x6f, 0x9b, 0x00, 0x18, 0x04
686 
	.byte	0x0c, 0xe2, 0x7e, 0x03, 0x54, 0x75, 0x00, 0x00, 0x3a, 0x52, 0x03, 0x02, 0x10
687 
	.byte	0x0c, 0xe3, 0x70, 0x55, 0x04, 0x73, 0x0e, 0x03, 0x25, 0xa3, 0x00, 0x10, 0x02
688 
	.byte	0x0c, 0xe4, 0x1a, 0x72, 0x33, 0x76, 0x00, 0x00, 0xeb, 0x97, 0x03, 0x05, 0x17
689 
	.byte	0x0c, 0xe5, 0x70, 0x36, 0x73, 0x12, 0x0a, 0x03, 0x79, 0xbe, 0x00, 0x17, 0x05
690 
	.byte	0x02, 0x3a, 0x06
691 
	.byte	0x01, 0x13
692 
	.byte	0x01, 0x29
693 
	.byte	0x80
694 
lcd_sequences_end:
695 
.endm
696 
 
697 
	mov	r0, #4
698 
	bl	sendlcdc
699 
	bl	readlcd
700 
	bl	readlcd
701 
	bl	readlcd
702 
	and	r0, r0, #3
703 
	ldr	r0, [sp,r0,lsl#2]
704 
	add	sp, sp, r0
705 
lcdloop:
706 
	ldrb	r1, [sp], #1
707 
	tst	r1, #0x80
708 
	beq	lcddata
709 
	bics	r1, r1, #0x80
710 
	beq	lcddone
711 
	mov	r0, r1,lsl#10
712 
	bl	udelay
713 
	b	lcdloop
714 
lcddata:
715 
	ldrb	r0, [sp], #1
716 
	bl	sendlcdc
717 
lcdbyte:
718 
	subs	r1, r1, #1
719 
	beq	lcdloop
720 
	ldrb	r0, [sp], #1
721 
	bl	sendlcdd
722 
	b	lcdbyte
723 
 
726 theseven 724 
values1:
725 
	block0_constpool
726 
	block1_constpool
727 
	gpio_initdata
728 
	pmu_batch_1
729 
	pmu_batch_2
730 
	pmu_batch_3
731 
	pmu_batch_4
732 
	pmu_batch_5
733 
	block6_constpool
734 
	lcd_sequences
735 
	.align	2
736 
 
737 
                           @ udelay register map:
738 
                           @ R0: Microseconds
739 
                           @ R1: Trashed
740 
                           @ R11: TIMER base address
725 theseven 741 
                           @ R14: Return address
742 
 
743 
udelay:
744 
	ldr	r1, [r11,#0xb4]
745 
	add	r0, r0, r1
746 
udelayloop:
747 
	ldr	r1, [r11,#0xb4]
748 
	cmp	r1, r0
749 
	bmi	udelayloop
750 
	mov	pc, lr
751 
 
726 theseven 752 
                           @ i2cwaitrdy register map:
753 
                           @ R9: Set to 0
754 
                           @ R10: I2C base address
725 theseven 755 
                           @ R14: Return address
756 
 
757 
i2cwaitrdy:
758 
	ldr	r9, [r10,#0x10]
759 
	cmp	r9, #0
760 
	bne	i2cwaitrdy
761 
	mov	pc, lr
762 
 
726 theseven 763 
                           @ i2cwait register map:
764 
                           @ R3: Set to 0x10
765 
                           @ R10: I2C base address
725 theseven 766 
                           @ R14: Return address
767 
 
768 
i2cwait:
769 
	ldr	r3, [r10]
770 
	ands	r3, #0x10
771 
	beq	i2cwait
772 
	mov	pc, lr
773 
 
726 theseven 774 
                           @ pmuwrite register map:
775 
                           @ R0: Address
776 
                           @ R1: Data
777 
                           @ R2: Set to 0xb7
778 
                           @ R3: Set to 0x10
779 
                           @ R4: Return address backup
780 
                           @ R10: I2C base address
725 theseven 781 
                           @ R14: Return address / Scratchpad
782 
 
783 
pmuwrite:
784 
	mov	r4, lr
785 
	mov	lr, #0xe6
786 
	str	lr, [r10,#0x0c]
787 
	mov	lr, #0xf0
788 
	str	lr, [r10,#0x04]
789 
	mov	r2, #0xb7
790 
	str	r2, [r10]
791 
	bl	i2cwait
792 
	str	r0, [r10,#0x0c]
793 
	str	r2, [r10]
794 
	bl	i2cwait
795 
	str	r1, [r10,#0x0c]
796 
	str	r2, [r10]
797 
	bl	i2cwait
798 
	mov	lr, #0xd0
799 
	str	lr, [r10,#0x04]
800 
	str	r2, [r10]
801 
pmuwrite_wait:
802 
	ldr	lr, [r10,#0x04]
803 
	tst	lr, #0x20
804 
	bne	pmuwrite_wait
805 
	mov	pc, r4
806 
 
726 theseven 807 
                           @ pmuread register map:
808 
                           @ R0: Address
809 
                           @ R1: Data
810 
                           @ R2: Set to 0xb7
811 
                           @ R3: Set to 0x10
812 
                           @ R4: Return address backup
813 
                           @ R10: I2C base address
725 theseven 814 
                           @ R14: Return address / Scratchpad
815 
 
816 
pmuread:
817 
	mov	r4, lr
818 
	mov	lr, #0xe6
819 
	str	lr, [r10,#0x0c]
820 
	mov	lr, #0xf0
821 
	str	lr, [r10,#0x04]
822 
	mov	r2, #0xb7
823 
	str	r2, [r10]
824 
	bl	i2cwait
825 
	str	r0, [r10,#0x0c]
826 
	str	r2, [r10]
827 
	bl	i2cwait
828 
	mov	r1, #0xe7
829 
	str	r1, [r10,#0x0c]
830 
	mov	r1, #0xb0
831 
	str	r1, [r10,#0x04]
832 
	str	r2, [r10]
833 
	bl	i2cwait
834 
	mov	r1, #0x37
835 
	str	r1, [r10]
836 
	bl	i2cwait
837 
	ldr	r1, [r10,#0x0c]
838 
	mov	lr, #0x90
839 
	str	lr, [r10,#0x04]
840 
	str	r2, [r10]
841 
pmuread_wait:
726 theseven 842 
	ldr	lr, [r10,#0x04]
843 
	tst	lr, #0x20
725 theseven 844 
	bne	pmuread_wait
845 
	mov	pc, r4
846 
 
726 theseven 847 
                           @ pmubatch register map:
848 
                           @ R0: Scratchpad
849 
                           @ R1: Scratchpad
850 
                           @ R2: Set to 0xb7
851 
                           @ R3: Set to 0x10
852 
                           @ R4: Inner return address backup
853 
                           @ R7: Outer return address backup
854 
                           @ R9: Number of address-data pairs to be sent (must be >0), will be reset to 0
855 
                           @ R10: I2C base address
725 theseven 856 
                           @ R13: Address-data pair list pointer (will be incremented)
857 
                           @ R14: Return address / Scratchpad
858 
 
859 
pmubatch:
860 
	mov	r7, lr
861 
pmubatch_loop:
862 
	ldrb	r0, [sp], #1
863 
	ldrb	r1, [sp], #1
864 
	bl	pmuwrite
865 
	subs	r9, r9, #1
866 
	bne	pmubatch_loop
867 
	mov	pc, r7
868 
 
726 theseven 869 
                           @ sendlcdc register map:
870 
                           @ R0: Command to be sent
871 
                           @ R8: LCD base address
872 
                           @ R9: Will be set to 0
725 theseven 873 
                           @ R14: Return address
874 
 
875 
sendlcdc:
876 
	ldr	r9, [r8,#0x1c]
877 
	ands	r9, r9, #0x10
878 
	bne	sendlcdc
879 
	str	r0, [r8,#0x04]
880 
	mov	pc, lr
881 
 
726 theseven 882 
                           @ sendlcdd register map:
883 
                           @ R0: Data to be sent
884 
                           @ R8: LCD base address
885 
                           @ R9: Will be set to 0
725 theseven 886 
                           @ R14: Return address
887 
 
888 
sendlcdd:
889 
	ldr	r9, [r8,#0x1c]
890 
	ands	r9, r9, #0x10
891 
	bne	sendlcdd
892 
	str	r0, [r8,#0x40]
893 
	mov	pc, lr
894 
 
726 theseven 895 
                           @ readlcd register map:
896 
                           @ R0: Result data
897 
                           @ R8: LCD base address
725 theseven 898 
                           @ R14: Return address
899 
 
900 
readlcd:
901 
	ldr	r0, [r8,#0x1c]
902 
	tst	r0, #2
903 
	beq	readlcd
904 
	str	r0, [r8,#0x10]
905 
readlcd_wait:
906 
	ldr	r0, [r8,#0x1c]
907 
	tst	r0, #0x1
908 
	beq	readlcd_wait
909 
	ldr	r0, [r8,#0x14]
910 
	mov	r0, r0,lsr#1
911 
	mov	pc, lr
912 
 
749 theseven 913 
lcd_mode:
914 
	.word	0x41100db8
915 
 
916 
 
725 theseven 917 
lcddone:
749 theseven 918 
	ldr	r0, lcd_mode
919 
	str	r0, [r8]
726 theseven 920 
	bic	r1, r10, #0x04400000
921 
	mov	r0, #1
922 
	str	r0, [r1,#0x30]
725 theseven 923 
	ldr	r0, _stubend
924 
	adr	r1, _stubend + 4
925 
	mov	r2, #0x08000000
926 
	add	r0, r1, r0
927 
movepayloadloop:
928 
	cmp	r0, r1
929 
	ldrhi	r3, [r1], #4
930 
	strhi	r3, [r2], #4
931 
	bhi	movepayloadloop
726 theseven 932 
	mcr	p15, 0, r9,c7,c14,0 @ clean data cache
725 theseven 933 
	mcr	p15, 0, r9,c7,c10,4 @ drain write buffer
726 theseven 934 
	mcr	p15, 0, r9,c7,c5,0  @ invalidate instruction cache
935 
	mcr	p15, 0, r9,c7,c5,4  @ flush prefetch buffer
725 theseven 936 
	mov	pc, #0x08000000
937 
 
938 
_stubend: