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725 theseven 1 
@
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@
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@    emCORE Loader for iPod Nano 4G
4 
@
5 
@    Copyright 2011 TheSeven, Farthen
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@
7 
@
8 
@    This file is part of emCORE.
9 
@
10 
@    emCORE is free software: you can redistribute it and/or
11 
@    modify it under the terms of the GNU General Public License as
12 
@    published by the Free Software Foundation, either version 2 of the
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@    License, or (at your option) any later version.
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@
15 
@    emCORE is distributed in the hope that it will be useful,
16 
@    but WITHOUT ANY WARRANTY; without even the implied warranty of
17 
@    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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@    See the GNU General Public License for more details.
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@
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@    You should have received a copy of the GNU General Public License along
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@    with emCORE.  If not, see <http://www.gnu.org/licenses/>.
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@
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@
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25 
.global _start
26 
_start:
27 
 
28 
	msr	cpsr_c, #0xd3
29 
	mrc	p15, 0, r0,c1,c0
30 
	bic	r0, r0, #1
31 
	mcr	p15, 0, r0,c1,c0 @ disable mmu
32 
 
33 
	mov	lr, #0
34 
	adr	sp, values1
35 
	mcr	p15, 0, lr,c7,c14,0 @ clean & invalidate data cache
36 
	mcr	p15, 0, lr,c7,c10,4 @ drain write buffer
37 
	mcr	p15, 0, lr,c7,c5    @ invalidate instruction cache
38 
	mcr	p15, 0, lr,c8,c7    @ invalidate all unlocked entries in the TLB
39 
	mcr	p15, 0, lr,c13,c0,0 @ disable context id register
40 
 
41 
.macro block0_constpool	   @ Block 0 (MMU, DMA) register map:
42 
                           @ R0: Unused
43 
                           @ R1: Unused
44 
                           @ R2: Unused
45 
                           @ R3: Scratchpad
46 
	                   @ R4: Unused
47 
	                   @ R5: Unused
48 
	                   @ R6: Unused
49 
	                   @ R7: Unused
50 
	                   @ R8: Unused
51 
	                   @ R9: Unused
52 
	.word	0x0005107D @ R10: CP15r1
53 
	.word	0x2202C000 @ R11: First level page table
54 
	.word	0x00000C1E @ R12: Default segment flags
55 
                           @ R13: Constant pool pointer
56 
.endm                      @ R14: 0
57 
 
58 
	ldmia	sp!, {r10-r12}
59 
	mcr	p15, 0, r11,c2,c0 @ set first level translation table
60 
	mov	r3, #-1
61 
	mcr	p15, 0, r3,c3,c0 @ disable domain access control                  @ R3: Unused
62 
mmuloop:
63 
	str	r12, [r11], #4
64 
	add	r12, r12, #0x00100000
65 
	cmp	r12, #0x38000000
66 
	biccs	r12, r12, #0xc
67 
	tst	r12, #0x40000000
68 
	beq	mmuloop
69 
                       								  @ R11: Unused
70 
    										  @ R12: Unused
71 
	mcr	p15, 0, r10,c1,c0                                                 @ R10: Unused
72 
 
73 
.macro block1_constpool	   @ Block 1 (SYSCON) register map:
74 
	.word	0x000327E5 @ R0: PWRCON(0)
75 
	.word	0xFE2BED6D @ R1: PWRCON(1)
76 
	.word	0x00DCF779 @ R2: PWRCON(4)
77 
	.word	0x003E3E00 @ R3
78 
	.word	0x06008501 @ R4
79 
	.word	0x00009DBC @ R5
80 
	.word	0x00404040 @ R6
81 
	.word	0x40001000 @ R7
82 
	.word	0x80008000 @ R8
83 
	.word	0x38501000 @ R9
84 
	.word	0xE02BED4D @ R10: PWRCON(1) during timer setup
85 
	.word	0x001CF700 @ R11: PWRCON(4) during timer setup
86 
	.word	0x3C500000 @ R12: SYSCON base address
87 
                           @ R13: Constant pool pointer
88 
.endm                      @ R14: 0
89 
 
90 
	ldmia	sp!, {r0-r12}
91 
	str	r0, [r12,#0x48]  @ PWRCON0 ...					  @ R0: Scratchpad
92 
	str	r1, [r12,#0x4c]
93 
	mov	r0, #0x73
94 
	str	r0, [r12,#0x58]
95 
	mov	r0, #0xff
96 
	str	r0, [r12,#0x68]
97 
	str	r2, [r12,#0x6c]  @ ... PWRCON4
98 
	str	lr, [r12]
99 
sysconwait1:
100 
	ldr	r0, [r12]
101 
	tst	r0, #0xf
102 
	bne	sysconwait1      @ while ([SYSCON] & 0xf)
103 
 
104 
	str	lr, [r12,#0x04]
105 
sysconwait2:
106 
	ldr	r0, [r12,#0x04]
107 
	tst	r0, r3
108 
	bne	sysconwait2      @ while ([SYSCON+4] & 0x003E3E00)
109 
 
110 
	mov	r0, #0x7
111 
	str	r0, [r12,#0x44]
112 
	str	lr, [r12,#0x44]
113 
	str	lr, [r12,#0x3c]
114 
	str	r4, [r12,#0x20]							  @ R4: Scratchpad
115 
	str	r5, [r12,#0x30]
116 
	mov	r5, #1                                                            @ R5: 1
117 
	str	r5, [r12,#0x44]
118 
	orr	r4, r0, #0x10000
119 
	str	r4, [r12,#0x44]
120 
sysconwait3:
121 
	ldr	r4, [r12,#0x40]
122 
	tst	r4, #0x1
123 
	beq	sysconwait3      @ while (!([SYSCON+0x40] & 1))
124 
 
125 
	str	r6, [r12,#0x04]							  @ R6: Unused
126 
	add	r3, r3, #0x3e                                                     @ R3: 0x003E3E3E
127 
sysconwait4:
128 
	ldr	r4, [r12,#0x04]
129 
	tst	r4, r3								  @ R3: Unused
130 
	bne	sysconwait4
131 
 
132 
	str	r7, [r12]							  @ R7: Unused
133 
sysconwait5:
134 
	ldr	r2, [r12]
135 
	tst	r4, #0xf
136 
	bne	sysconwait5
137 
 
138 
	str	r8, [r12,#0x08]
139 
	orr	r4, r8, r8,lsr#1						  @ R8: Unused
140 
	str	r4, [r12,#0x0c]
141 
	mov	r4, #0xc000
142 
	str	r4, [r12,#0x10]
143 
	mov	r4, #0x8000
144 
	str	r4, [r12,#0x14]
145 
	str	r4, [r12,#0x70]
146 
	mov	r4, #2
147 
	str	r4, [r9]                                                          @ R9: Unused
148 
	mov	r0, #0x10                                                         @ R5: 0x10
149 
 
150 
	                   @ Block 2 (TIMER) register map:
151 
	                   @ R0: 1
152 
	                   @ R1: PWRCON(1)
153 
	                   @ R2: PWRCON(4)
154 
	                   @ R3: Scratchpad
155 
	                   @ R4: Scratchpad
156 
	                   @ R5: 0x10
157 
	                   @ R6: Unused
158 
	                   @ R7: Unused
159 
	                   @ R8: Unused
160 
	                   @ R9: Unused
161 
	                   @ R10: PWRCON(1) during timer setup
162 
	                   @ R11: PWRCON(4) during timer setup
163 
	                   @ R12: SYSCON base address
164 
                           @ R13: Constant pool pointer
165 
                           @ R14: 0
166 
 
167 
	str	r10, [r12,#0x4c]     @ PWRCON(1) for timer setup                  @ R10: Unused
168 
	mov	r4, #0x13
169 
	str	r4, [r12,#0x58]	     @ PWRCON(2) for timer setup
170 
	str	r11, [r12,#0x6c]     @ PWRCON(4) for timer setup                  @ R11: Unused
171 
	orr     r11, r12, #0x00200000                                             @ R11: TIMER base address
172 
	str	r0, [r11,#0x4]       @ TACMD = 0x10
173 
	str	r0, [r11,#0x24]      @ TBCMD = 0x10
174 
	str	r0, [r11,#0x44]      @ TCCMD = 0x10
175 
	str	r0, [r11,#0x64]      @ TDCMD = 0x10
176 
	mov	r3, #0x40
177 
	str	r3, [r11,#0xa0]      @ TECON = 0x40
178 
	mov	r3, #0xb
179 
	str	r3, [r11,#0xb0]      @ TEPRE = 0xb
180 
	mov	r4, #-1                                                           @ R4: -1
181 
	str	r4, [r11,#0xa8]      @ TEDATA0 = 0xFFFFFFFF
182 
	mov	r3, #0x3
183 
	str	r3, [r11,#0xa4]      @ TECMD = 0x3
184 
	str	r0, [r11,#0xc4]      @ TFCMD = 0x10
185 
	str	r0, [r11,#0xe4]      @ TGCMD = 0x10
186 
	str	r0, [r11,#0x104]     @ THCMD = 0x10
187 
	str	r4, [r11,#0x118]     @ THCMD = 0xFFFFFFFF
188 
	str	r1, [r12,#0x4c]      @ PWRCON(1)                                  @ R1: Unused
189 
	mov	r3, #0x73
190 
	str	r3, [r12,#0x58]      @ PWRCON(2)
191 
	str	r2, [r12,#0x6c]      @ PWRCON(4)				  @ R2: Unused
192 
	orr	r10, r11, #0x00800000                                             @ R10: GPIO base address
193 
 
194 
	                   @ Block 3 (GPIO) register map:
195 
	                   @ R0: Unused
196 
	                   @ R1: Unused
197 
	                   @ R2: Unused
198 
	                   @ R3: Scratchpad
199 
	                   @ R4: -1
200 
	                   @ R5: 1
201 
	                   @ R6: Unused
202 
	                   @ R7: Unused
203 
	                   @ R8: Unused
204 
	                   @ R9: Unused
205 
	                   @ R10: GPIO base address
206 
	                   @ R11: TIMER base address
207 
	                   @ R12: SYSCON base address
208 
                           @ R13: Constant pool pointer
209 
                           @ R14: 0
210 
 
211 
.macro gpio_initdata
212 
	.word	0x3202EEEE @ PCON0
213 
	.word	0xE0EE2253 @ PCON1
214 
	.word	0x2223EEEE @ PCON2
215 
	.word	0x33333332 @ PCON3
216 
	.word	0xFF333E33 @ PCON4
217 
	.word	0xE0FEE200 @ PCON5
218 
	.word	0x2222222E @ PCON6
219 
	.word	0x22222222 @ PCON7
220 
	.word	0xEEEEEEE2 @ PCON8
221 
	.word	0xEEE0EEEE @ PCON9
222 
	.word	0x2EEEEEEE @ PCONA
223 
	.word	0xEEEE0222 @ PCONB
224 
	.word	0xEEEEE00E @ PCONC
225 
	.word	0xEEEEEEEE @ PCOND
226 
	.word	0xEEEEEEEE @ PCONE
227 
.endm
228 
 
229 
	ldr	r3, [sp], #0x4
230 
	str	r3, [r10], #0xc                                       		  @ R10: PCONx iterator
231 
	mov	r3, #0x20
232 
	str	r3, [r10], #0x4     @ PCON0 + 0xc = 0x20
233 
	mov	r3, #0x40
234 
	str	r3, [r10], #0x10    @ PCON0 + 0x10 = 0x40
235 
	add	r9, r10, #0x1a0                                                   @ R9: Iterator limit
236 
gpioloop1:
237 
	ldr	r3, [sp], #0x4
238 
	str	r3, [r10], #0xc
239 
	str	lr, [r10], #0x4     @ PCON + 0xc = 0
240 
	str	lr, [r10], #0x10    @ PCON + 0x10 = 0
241 
	cmp	r10, r9
242 
	bls	gpioloop1
243 
										  @ R10: 0x3CF001E0
244 
	ldr	r3, [r10,#0x1a8]
245 
	bic	r3, r3, #2
246 
	orr	r3, r3, #1
247 
	str	r3, [r10,#0x1a8]
248 
	sub	r8, r11, #0x00300000                                              @ R8: 0x39700000 (iterator)
249 
	mov	r9, #6                                                            @ R9: Iterations remaining
250 
gpioloop2:
251 
	str	r14, [r8,#0x80]
252 
	str	r4, [r8,#0xa0]
253 
	str	r14, [r8,#0xc0]
254 
	str	r14, [r8,#0xe0]
255 
	add	r8, r8, #4
256 
	subs	r9, r9, #1
257 
	bne	gpioloop2
258 
    										  @ R9: 0
259 
	ldr	r8, [r10,#-0x180]						  @ R8: PCON3 backup
260 
	and	r3, r8, #0xff
261 
	str	r3, [r10,#-0x180]   @ *PCON3 &= 0xff
262 
	mov	r0, #0x3e8							  @ R0: Scratchpad
263 
	bl	udelay	                                                          @ R14: Return address
264 
	ldr	r3, [r10,#-0x17c]
265 
	and	r3, r3, #0xfc
266 
	mov	r6, r3, lsr #0x2                                                  @ R6: Data for first PMU access
267 
	str	r8, [r10,#-0x180]
268 
	bic	r10, r11, #0x00100000                                             @ R10: I2C base address
269 
 
270 
	                   @ Block 4 (I2C) register map:
271 
	                   @ R0: Scratchpad
272 
	                   @ R1: Scratchpad
273 
	                   @ R2: Unused
274 
	                   @ R3: Unused
275 
	                   @ R4: -1
276 
	                   @ R5: 1
277 
	                   @ R6: Data for first PMU access
278 
	                   @ R7: Unused
279 
	                   @ R8: Unused
280 
	                   @ R9: 0
281 
	                   @ R10: I2C base address
282 
	                   @ R11: TIMER base address
283 
	                   @ R12: SYSCON base address
284 
                           @ R13: Constant pool pointer
285 
                           @ R14: Return address / Scratchpad
286 
 
287 
	bl	i2cwaitrdy
288 
	mov	r1, #0x40
289 
	str	r1, [r10,#0x08]
290 
	bl	i2cwaitrdy
291 
	str	r5, [r10,#0x14]
292 
	bl	i2cwaitrdy
293 
	str	r9, [r10,#0x18]
294 
	bl	i2cwaitrdy
295 
	mov	r0, #0x80
296 
	str	r0, [r10,#0x04]
297 
	bl	i2cwaitrdy
298 
	str	r9, [r10]
299 
	bl	i2cwaitrdy
300 
	str	r9, [r10,#0x04]
301 
	bl	i2cwaitrdy
302 
	str	r1, [r10,#0x0c]
303 
	bl	i2cwaitrdy
304 
	orr	r0, r5, #0x180
305 
	str	r0, [r10]
306 
	bl	i2cwaitrdy
307 
	mov	r0, #0x10
308 
	str	r0, [r10,#0x04]
309 
	bl	i2cwaitrdy
310 
 
311 
	                   @ Block 5 (PMU) register map:
312 
	                   @ R0: Address / Scratchpad (trashed by pmubatch)
313 
	                   @ R1: Data / Scratchpad (trashed by pmubatch)
314 
	                   @ R2: Scratchpad (set to 0xb7 by pmu accesses)
315 
	                   @ R3: Scratchpad (set to 0x10 by pmu accesses)
316 
	                   @ R4: Scratchpad (trashed by pmu accesses)
317 
	                   @ R5: 1
318 
	                   @ R6: Data for first PMU access
319 
	                   @ R7: Scratchpad (trashed by pmubatch)
320 
	                   @ R8: Used to store warmboot flag
321 
	                   @ R9: 0 / pmubatch transfer count (reset to 0 by pmubatch)
322 
	                   @ R10: I2C base address
323 
	                   @ R11: TIMER base address
324 
	                   @ R12: SYSCON base address
325 
                           @ R13: Constant pool / pmubatch data pointer
326 
                           @ R14: Return address / Scratchpad
327 
 
328 
	mov	r0, #0x7f
329 
	mov	r1, r6
330 
	bl	pmuwrite
331 
	mov	r0, #0x02
332 
	bl	pmuread
333 
	ands	r8, r1, #0x80                                                     @ R8: Warmboot flag
334 
	beq	pmu_coldboot
335 
	mov	r1, #0x80
336 
	bl	pmuwrite
337 
pmu_coldboot:
338 
.macro pmu_batch_1
339 
pmu_batch_1_begin:
340 
	.byte	0x14, 0x13
341 
	.byte	0x15, 0x0d
342 
	.byte	0x0b, 0x22
343 
pmu_batch_1_end:
344 
.endm
345 
	mov	r9, #(pmu_batch_1_end - pmu_batch_1_begin) / 2
346 
	bl	pmubatch
347 
	tst	r6, #1							          @ R6: Unused
348 
	beq	pmu_skip
349 
	mov	r0, #0x0d
350 
	bl	pmuread
351 
	and	r1, r1, #0xdf
352 
	bl	pmuwrite
353 
pmu_skip:
354 
.macro pmu_batch_2
355 
pmu_batch_2_begin:
356 
	.byte	0x1f, 0x14
357 
	.byte	0x1a, 0xb2
358 
	.byte	0x1a, 0xb2
359 
	.byte	0x19, 0x14
360 
	.byte	0x21, 0x06
361 
	.byte	0x1d, 0x12
362 
pmu_batch_2_end:
363 
.endm
364 
	mov	r9, #(pmu_batch_2_end - pmu_batch_2_begin) / 2
365 
	bl	pmubatch
366 
	mov	r0, #0x10
367 
	bl	pmuread
368 
	bic	r1, r1, #0x80
369 
	orr	r1, r1, #0x60
370 
nop@	bl	pmuwrite
371 
.macro pmu_batch_3
372 
pmu_batch_3_begin:
373 
	.byte	0x44, 0x72
374 
pmu_batch_3_end:
375 
.endm
376 
	mov	r9, #(pmu_batch_3_end - pmu_batch_3_begin) / 2
377 
	bl	pmubatch
378 
	mov	r0, #0x40
379 
	bl	pmuread
380 
	orr	r1, r1, #0x40
381 
	bl	pmuwrite
382 
	mov	r0, #0x33
383 
	bl	pmuread
384 
	and	r1, r1, #0x03
385 
	orr	r1, r1, #0x50
386 
	bl	pmuwrite
387 
	mov	r0, #0x34
388 
	bl	pmuread
389 
	and	r1, r1, #0x80
390 
	orr	r1, r1, #0x54
391 
	bl	pmuwrite
392 
.macro pmu_batch_4
393 
pmu_batch_4_begin:
394 
	.byte	0x22, 0x00
395 
	.byte	0x07, 0x50
396 
	.byte	0x08, 0xfe
397 
	.byte	0x09, 0x2b
398 
	.byte	0x01, 0xff
399 
	.byte	0x02, 0xff
400 
	.byte	0x03, 0xff
401 
pmu_batch_4_end:
402 
.endm
403 
	mov	r9, #(pmu_batch_4_end - pmu_batch_4_begin) / 2
404 
	bl	pmubatch
405 
	cmp	r8, #0
406 
	bne	pmu_warmboot
407 
	mov	r0, #0x30
408 
	mov	r1, #0x64
409 
	bl	pmuwrite
410 
pmu_warmboot:
411 
	mov	r0, #0x31
412 
	bl	pmuread
413 
	bic	r1, r1, #0x01
414 
	bl	pmuwrite
415 
.macro pmu_batch_5
416 
pmu_batch_5_begin:
417 
	.byte	0x0a, 0x70
418 
	.byte	0x13, 0x02
419 
pmu_batch_5_end:
420 
.endm
421 
	mov	r9, #(pmu_batch_5_end - pmu_batch_5_begin) / 2
422 
	bl	pmubatch
423 
 
424 
	orr	lr, r11, #0x00800000						  @ R14: GPIO base address
425 
	str	r9, [lr,#0x384]
426 
	orr	lr, r11, #0x01000000						  @ R14: MIU base address
427 
	str	r5, [lr]
428 
	ldrh	r0, [sp], #2
429 
	str	r0, [lr,#0x100]
430 
	mov	r0, #0xff
431 
	str	r0, [lr,#0x11c]
432 
	str	r0, [lr,#0x120]
433 
 
434 
.macro block6_constpool	   @ Block 6 (SDRAM) register map:
435 
	.hword	0x1030
436 
	.word	0x008AAC25 @ R0
437 
	.word	0x050D67E5 @ R1
438 
	.word	0x0002000B @ R2
439 
	.word	0x0003B3B2 @ R3
440 
	.word	0xFF53B3B0 @ R4
441 
	.word	0x00008040 @ R5
442 
	.word	0x8000100F @ R6: For LCD init at end of block
443 
	.word	0x41100DB8 @ R7: For LCD init at end of block
444 
	                   @ R8: Warmboot flag
445 
	                   @ R9: 0
446 
	                   @ R10: I2C base address
447 
	                   @ R11: TIMER base address
448 
	                   @ R12: SYSCON base address
449 
                           @ R13: Constant pool pointer
450 
.endm                      @ R14: MIU base address
451 
 
452 
	ldmia	sp!, {r0-r7}
453 
	str	r0, [lr,#0x114]							  @ R0: Unused
454 
	str	r1, [lr,#0x124]							  @ R1: Unused
455 
	mov	r0, #0x18							  @ R0: Scratchpad
456 
	str	r0, [lr,#0x118]
457 
	str	r2, [lr,#0x108]
458 
	mov	r0, #4
459 
	str	r0, [lr,#0x148]
460 
	str	r9, [lr,#0x14c]
461 
	str	r3, [lr,#0x140]
462 
miu_wait1:
463 
	ldr	r0, [lr,#0x140]
464 
	tst	r0, #2
465 
	beq	miu_wait1
466 
	add	r0, r3, #1							  @ R3: Unused
467 
	str	r0, [lr,#0x140]
468 
miu_wait2:
469 
	ldr	r0, [lr,#0x144]
470 
	mvn	r0, r0
471 
	tst	r0, #3
472 
	bne	miu_wait2
473 
	ldr	r1, [lr,#0x144]			                                  @ R1: Scratchpad
474 
	mov	r0, #0x0ff00000
475 
	and	r0, r0, r1, lsl #0x2
476 
	add	r0, r0, r4	                                                  @ R4: Unused
477 
	str	r0, [lr,#0x140]
478 
	mov	r0, #0x10
479 
	str	r0, [lr,#0x150]
480 
	cmp	r8, #0								  @ R8: Unused
481 
	sub	r8, r10, #0x04300000                                              @ R8: LCD base address
482 
	str	r6, [r12,#0x08]                                                   @ R6: Unused
483 
	str	r7, [r8]                                                          @ R7: Unused
484 
	mov	r0, #0x11
485 
	str	r0, [r8,#0x20]
486 
	mov	r3, #0x33							  @ R3: 0x33
487 
	beq	miu_coldboot
488 
	str	r0, [lr,#0x104]
489 
	b	miu_common
490 
miu_coldboot:
491 
	str	r3, [lr,#0x104]
492 
	orr	r0, r3, #0x200
493 
	str	r0, [lr,#0x104]
494 
miu_wait3:
495 
	ldr	r0, [lr,#0x104]
496 
	tst	r0, #0x110000
497 
	bne	miu_wait3
498 
	str	r3, [lr,#0x104]
499 
	str	r3, [lr,#0x104]
500 
	str	r3, [lr,#0x104]
501 
	orr	r1, r3, #0x300
502 
	str	r1, [lr,#0x104]
503 
miu_wait4:
504 
	ldr	r0, [lr,#0x104]
505 
	tst	r0, #0x110000
506 
	bne	miu_wait4
507 
	str	r3, [lr,#0x104]
508 
	str	r3, [lr,#0x104]
509 
	str	r3, [lr,#0x104]
510 
	str	r1, [lr,#0x104]
511 
miu_wait5:
512 
	ldr	r0, [lr,#0x104]
513 
	tst	r0, #0x110000
514 
	bne	miu_wait5
515 
	str	r3, [lr,#0x104]
516 
	str	r3, [lr,#0x104]
517 
	str	r3, [lr,#0x104]
518 
	str	r3, [lr,#0x110]
519 
	orr	r1, r3, #0x100
520 
	str	r1, [lr,#0x104]
521 
miu_wait6:
522 
	ldr	r0, [lr,#0x104]
523 
	tst	r0, #0x110000
524 
	bne	miu_wait6
525 
	str	r3, [lr,#0x104]
526 
	str	r3, [lr,#0x104]
527 
	str	r3, [lr,#0x104]
528 
	str	r5, [lr,#0x110]							  @ R5: Unused
529 
	str	r1, [lr,#0x104]
530 
miu_wait7:
531 
	ldr	r0, [lr,#0x104]
532 
	tst	r0, #0x110000
533 
	bne	miu_wait7
534 
	str	r3, [lr,#0x104]
535 
	str	r3, [lr,#0x104]
536 
miu_common:
537 
	str	r3, [lr,#0x104]							  @ R3: Unused
538 
	mov	r0, #0x40
539 
	str	r0, [lr,#0x10c]
540 
	ldr	r0, [lr,#0x100]
541 
	orr	r0, r0, #0x9100000
542 
	str	r0, [lr,#0x100]
543 
	mov	r0, #0x19
544 
	str	r0, [lr,#0x11c]
545 
	mov	r0, #1
546 
	str	r0, [lr,#0x120]
547 
	orr	r1, r2, #0x1000							  @ R2: Unused
548 
	str	r1, [lr,#0x108]
549 
	str	r0, [lr,#0x08]
550 
	mov	r1, #0x3e000000
551 
	mov	r0, #0x1f
552 
	str	r0, [r1,#0x08]
553 
 
554 
                           @ Block 7 (LCD) register map:
555 
	                   @ R0: Cmd/Data to be written / Scratchpad
556 
                           @ R1: Scratchpad
557 
                           @ R2: Scratchpad
558 
                           @ R3: Scratchpad
559 
                           @ R4: Scratchpad
560 
                           @ R5: Scratchpad
561 
                           @ R6: Unused
562 
                           @ R7: Unused
563 
	                   @ R8: LCD base address
564 
	                   @ R9: 0
565 
	                   @ R10: I2C base address
566 
	                   @ R11: TIMER base address
567 
	                   @ R12: SYSCON base address
568 
                           @ R13: LCD init script pointer / Scratchpad
569 
                           @ R14: Return address / Scratchpad
570 
 
571 
.macro lcd_sequences
572 
lcd_sequences_begin:
573 
	.word	lcd_sequence_c4 - lcd_sequences_begin
574 
	.word	lcd_sequence_d5 - lcd_sequences_begin
575 
	.word	lcd_sequence_e6 - lcd_sequences_begin
576 
	.word	lcd_sequence_b3 - lcd_sequences_begin
577 
lcd_sequence_b3:
578 
	.byte	0x01, 0x11
579 
	.byte	0xf8
580 
	.byte	0x02, 0xfe, 0x00
581 
	.byte	0x02, 0xef, 0x80
582 
	.byte	0x02, 0xc0, 0x0c
583 
	.byte	0x02, 0xc1, 0x03
584 
	.byte	0x03, 0xc2, 0x12, 0x00
585 
	.byte	0x03, 0xc3, 0x12, 0x00
586 
	.byte	0x03, 0xc4, 0x12, 0x00
587 
	.byte	0x03, 0xc5, 0x3a, 0x3e
588 
	.byte	0x03, 0xb1, 0x6a, 0x15
589 
	.byte	0x03, 0xb2, 0x5f, 0x3f
590 
	.byte	0x03, 0xb3, 0x5f, 0x3f
591 
	.byte	0x02, 0xb4, 0x02
592 
	.byte	0x03, 0xb6, 0x12, 0x02
593 
	.byte	0x02, 0x35, 0x00
594 
	.byte	0x02, 0x26, 0x10
595 
	.byte	0x0c, 0xe0, 0x0f, 0x42, 0x24, 0x01, 0x00, 0x02, 0xa6, 0x98, 0x05, 0x04, 0x15
596 
	.byte	0x0c, 0xe1, 0x00, 0x21, 0x44, 0x02, 0x0f, 0x05, 0x89, 0x6a, 0x02, 0x15, 0x04
597 
	.byte	0x0c, 0xe2, 0x7e, 0x04, 0x43, 0x40, 0x00, 0x02, 0x13, 0x00, 0x00, 0x01, 0x0b
598 
	.byte	0x0c, 0xe3, 0x40, 0x40, 0x03, 0x74, 0x0e, 0x00, 0x00, 0x31, 0x02, 0x0b, 0x01
599 
	.byte	0x0c, 0xe4, 0x5a, 0x43, 0x67, 0x56, 0x00, 0x02, 0x67, 0x72, 0x00, 0x05, 0x12
600 
	.byte	0x0c, 0xe5, 0x50, 0x66, 0x47, 0x53, 0x0a, 0x00, 0x27, 0x76, 0x02, 0x12, 0x02
601 
	.byte	0x02, 0x3a, 0x06
602 
	.byte	0x01, 0x13
603 
	.byte	0x01, 0x29
604 
	.byte	0x80
605 
lcd_sequence_c4:
606 
	.byte	0x01, 0x01
607 
	.byte	0x85
608 
	.byte	0x02, 0xc0, 0x00
609 
	.byte	0x02, 0xc1, 0x03
610 
	.byte	0x02, 0xc2, 0x34
611 
	.byte	0x03, 0xc3, 0x72, 0x03
612 
	.byte	0x03, 0xc4, 0x73, 0x03
613 
	.byte	0x03, 0xc5, 0x3c, 0x3c
614 
	.byte	0x02, 0xfe, 0x00
615 
@	.byte	0x03, 0xb1, 0x6a, 0x15
616 
	.byte	0x03, 0xb2, 0x6a, 0x15
617 
	.byte	0x03, 0xb3, 0x6a, 0x15
618 
	.byte	0x02, 0xb4, 0x02
619 
	.byte	0x03, 0xb6, 0x12, 0x02
620 
	.byte	0x02, 0x35, 0x00
621 
	.byte	0x02, 0x26, 0x10
622 
	.byte	0x0c, 0xe0, 0x77, 0x52, 0x76, 0x53, 0x03, 0x03, 0x57, 0x42, 0x10, 0x18, 0x09
623 
	.byte	0x0c, 0xe1, 0x0d, 0x00, 0x23, 0x66, 0x0f, 0x15, 0x4d, 0x85, 0x08, 0x02, 0x10
624 
	.byte	0x0c, 0xe2, 0x39, 0x60, 0x77, 0x05, 0x03, 0x07, 0x96, 0x64, 0x0d, 0x1a, 0x0a
625 
	.byte	0x0c, 0xe3, 0x3f, 0x10, 0x16, 0x44, 0x0e, 0x04, 0x6c, 0x44, 0x04, 0x03, 0x0b
626 
	.byte	0x0c, 0xe4, 0x00, 0x61, 0x77, 0x04, 0x02, 0x04, 0x72, 0x32, 0x09, 0x19, 0x06
627 
	.byte	0x0c, 0xe5, 0x4f, 0x42, 0x27, 0x67, 0x0f, 0x02, 0x26, 0x33, 0x01, 0x03, 0x09
628 
@	.byte	0x02, 0x3a, 0x66
629 
	.byte	0x02, 0x36, 0x00
630 
	.byte	0x01, 0x11
631 
	.byte	0x01, 0x29
632 
	.byte	0x80
633 
lcd_sequence_d5:
634 
	.byte	0x02, 0xfe, 0x00
635 
	.byte	0x02, 0xc0, 0x01
636 
	.byte	0x02, 0xc1, 0x01
637 
	.byte	0x03, 0xc2, 0x03, 0x00
638 
	.byte	0x03, 0xc3, 0x01, 0x00
639 
	.byte	0x03, 0xc4, 0x03, 0x00
640 
	.byte	0x03, 0xc5, 0x34, 0x34
641 
	.byte	0x02, 0xc7, 0x00
642 
	.byte	0x03, 0xb1, 0x6d, 0x15
643 
	.byte	0x03, 0xb2, 0x6d, 0x15
644 
	.byte	0x03, 0xb3, 0x6d, 0x15
645 
	.byte	0x02, 0xb4, 0x03
646 
	.byte	0x03, 0xb6, 0x11, 0x02
647 
	.byte	0x02, 0x35, 0x00
648 
	.byte	0x02, 0x26, 0x10
649 
	.byte	0x0c, 0xe0, 0x23, 0x42, 0x20, 0x42, 0x0e, 0x01, 0xf5, 0xeb, 0x1e, 0x05, 0x18
650 
	.byte	0x0c, 0xe1, 0x5f, 0x22, 0x36, 0x21, 0x03, 0x1e, 0xfe, 0x7b, 0x02, 0x07, 0x18
651 
	.byte	0x0c, 0xe2, 0x5f, 0x34, 0x53, 0x77, 0x0a, 0x00, 0x70, 0xf4, 0x14, 0x06, 0x0f
652 
	.byte	0x0c, 0xe3, 0x0f, 0x23, 0x31, 0x54, 0x0f, 0x0b, 0x8e, 0x08, 0x00, 0x05, 0x15
653 
	.byte	0x0c, 0xe4, 0x5f, 0x33, 0x42, 0x14, 0x0e, 0x04, 0xa6, 0xf7, 0x0e, 0x00, 0x14
654 
	.byte	0x0c, 0xe5, 0x0c, 0x43, 0x44, 0x44, 0x0d, 0x0d, 0x7f, 0x39, 0x03, 0x02, 0x10
655 
	.byte	0x02, 0x3a, 0x66
656 
	.byte	0x02, 0x36, 0x00
657 
	.byte	0x01, 0x11
658 
	.byte	0x01, 0x29
659 
	.byte	0x80
660 
lcd_sequence_e6:
661 
	.byte	0x01, 0x11
662 
	.byte	0xf8
663 
	.byte	0x02, 0xfe, 0x00
664 
	.byte	0x02, 0xef, 0x80
665 
	.byte	0x02, 0xc0, 0x13
666 
	.byte	0x02, 0xc1, 0x03
667 
	.byte	0x03, 0xc2, 0x12, 0x00
668 
	.byte	0x03, 0xc3, 0x12, 0x00
669 
	.byte	0x03, 0xc4, 0x12, 0x00
670 
	.byte	0x03, 0xc5, 0x2a, 0x3c
671 
	.byte	0x03, 0xb1, 0x6a, 0x15
672 
	.byte	0x03, 0xb2, 0x5f, 0x3f
673 
	.byte	0x03, 0xb3, 0x5f, 0x3f
674 
	.byte	0x02, 0xb4, 0x02
675 
	.byte	0x03, 0xb6, 0x12, 0x02
676 
	.byte	0x02, 0x35, 0x00
677 
	.byte	0x02, 0x26, 0x10
678 
	.byte	0x0c, 0xe0, 0x0f, 0x53, 0x45, 0x07, 0x00, 0x00, 0xb9, 0xf6, 0x08, 0x04, 0x18
679 
	.byte	0x0c, 0xe1, 0x00, 0x47, 0x55, 0x03, 0x0f, 0x08, 0x6f, 0x9b, 0x00, 0x18, 0x04
680 
	.byte	0x0c, 0xe2, 0x7e, 0x03, 0x54, 0x75, 0x00, 0x00, 0x3a, 0x52, 0x03, 0x02, 0x10
681 
	.byte	0x0c, 0xe3, 0x70, 0x55, 0x04, 0x73, 0x0e, 0x03, 0x25, 0xa3, 0x00, 0x10, 0x02
682 
	.byte	0x0c, 0xe4, 0x1a, 0x72, 0x33, 0x76, 0x00, 0x00, 0xeb, 0x97, 0x03, 0x05, 0x17
683 
	.byte	0x0c, 0xe5, 0x70, 0x36, 0x73, 0x12, 0x0a, 0x03, 0x79, 0xbe, 0x00, 0x17, 0x05
684 
	.byte	0x02, 0x3a, 0x06
685 
	.byte	0x01, 0x13
686 
	.byte	0x01, 0x29
687 
	.byte	0x80
688 
lcd_sequences_end:
689 
.endm
690 
 
691 
	mov	r0, #4
692 
	bl	sendlcdc
693 
	bl	readlcd
694 
	bl	readlcd
695 
	bl	readlcd
696 
	and	r0, r0, #3
697 
	ldr	r0, [sp,r0,lsl#2]
698 
	add	sp, sp, r0
699 
lcdloop:
700 
	ldrb	r1, [sp], #1
701 
	tst	r1, #0x80
702 
	beq	lcddata
703 
	bics	r1, r1, #0x80
704 
	beq	lcddone
705 
	mov	r0, r1,lsl#10
706 
	bl	udelay
707 
	b	lcdloop
708 
lcddata:
709 
	ldrb	r0, [sp], #1
710 
	bl	sendlcdc
711 
lcdbyte:
712 
	subs	r1, r1, #1
713 
	beq	lcdloop
714 
	ldrb	r0, [sp], #1
715 
	bl	sendlcdd
716 
	b	lcdbyte
717 
 
718 
	                   @ udelay register map:
719 
	                   @ R0: Microseconds
720 
	                   @ R1: Trashed
721 
	                   @ R11: TIMER base address
722 
                           @ R14: Return address
723 
 
724 
udelay:
725 
	ldr	r1, [r11,#0xb4]
726 
	add	r0, r0, r1
727 
udelayloop:
728 
	ldr	r1, [r11,#0xb4]
729 
	cmp	r1, r0
730 
	bmi	udelayloop
731 
	mov	pc, lr
732 
 
733 
	                   @ i2cwaitrdy register map:
734 
	                   @ R9: Set to 0
735 
	                   @ R10: I2C base address
736 
                           @ R14: Return address
737 
 
738 
i2cwaitrdy:
739 
	ldr	r9, [r10,#0x10]
740 
	cmp	r9, #0
741 
	bne	i2cwaitrdy
742 
	mov	pc, lr
743 
 
744 
	                   @ i2cwait register map:
745 
	                   @ R3: Set to 0x10
746 
	                   @ R10: I2C base address
747 
                           @ R14: Return address
748 
 
749 
i2cwait:
750 
	ldr	r3, [r10]
751 
	ands	r3, #0x10
752 
	beq	i2cwait
753 
	mov	pc, lr
754 
 
755 
	                   @ pmuwrite register map:
756 
	                   @ R0: Address
757 
	                   @ R1: Data
758 
			   @ R2: Set to 0xb7
759 
	                   @ R3: Set to 0x10
760 
	                   @ R4: Return address backup
761 
	                   @ R10: I2C base address
762 
                           @ R14: Return address / Scratchpad
763 
 
764 
pmuwrite:
765 
	mov	r4, lr
766 
	mov	lr, #0xe6
767 
	str	lr, [r10,#0x0c]
768 
	mov	lr, #0xf0
769 
	str	lr, [r10,#0x04]
770 
	mov	r2, #0xb7
771 
	str	r2, [r10]
772 
	bl	i2cwait
773 
	str	r0, [r10,#0x0c]
774 
	str	r2, [r10]
775 
	bl	i2cwait
776 
	str	r1, [r10,#0x0c]
777 
	str	r2, [r10]
778 
	bl	i2cwait
779 
	mov	lr, #0xd0
780 
	str	lr, [r10,#0x04]
781 
	str	r2, [r10]
782 
pmuwrite_wait:
783 
	ldr	lr, [r10,#0x04]
784 
	tst	lr, #0x20
785 
	bne	pmuwrite_wait
786 
	mov	pc, r4
787 
 
788 
	                   @ pmuread register map:
789 
	                   @ R0: Address
790 
	                   @ R1: Data
791 
			   @ R2: Set to 0xb7
792 
	                   @ R3: Set to 0x10
793 
	                   @ R4: Return address backup
794 
	                   @ R10: I2C base address
795 
                           @ R14: Return address / Scratchpad
796 
 
797 
pmuread:
798 
	mov	r4, lr
799 
	mov	lr, #0xe6
800 
	str	lr, [r10,#0x0c]
801 
	mov	lr, #0xf0
802 
	str	lr, [r10,#0x04]
803 
	mov	r2, #0xb7
804 
	str	r2, [r10]
805 
	bl	i2cwait
806 
	str	r0, [r10,#0x0c]
807 
	str	r2, [r10]
808 
	bl	i2cwait
809 
	mov	r1, #0xe7
810 
	str	r1, [r10,#0x0c]
811 
	mov	r1, #0xb0
812 
	str	r1, [r10,#0x04]
813 
	str	r2, [r10]
814 
	bl	i2cwait
815 
	mov	r1, #0x37
816 
	str	r1, [r10]
817 
	bl	i2cwait
818 
	ldr	r1, [r10,#0x0c]
819 
	mov	lr, #0x90
820 
	str	lr, [r10,#0x04]
821 
	str	r2, [r10]
822 
pmuread_wait:
823 
	ldr	r1, [r10,#0x04]
824 
	tst	r1, #0x20
825 
	bne	pmuread_wait
826 
	mov	pc, r4
827 
 
828 
	                   @ pmubatch register map:
829 
	                   @ R0: Scratchpad
830 
	                   @ R1: Scratchpad
831 
			   @ R2: Set to 0xb7
832 
	                   @ R3: Set to 0x10
833 
	                   @ R4: Inner return address backup
834 
			   @ R7: Outer return address backup
835 
			   @ R9: Number of address-data pairs to be sent (must be >0), will be reset to 0
836 
	                   @ R10: I2C base address
837 
                           @ R13: Address-data pair list pointer (will be incremented)
838 
                           @ R14: Return address / Scratchpad
839 
 
840 
pmubatch:
841 
	mov	r7, lr
842 
pmubatch_loop:
843 
	ldrb	r0, [sp], #1
844 
	ldrb	r1, [sp], #1
845 
	bl	pmuwrite
846 
	subs	r9, r9, #1
847 
	bne	pmubatch_loop
848 
	mov	pc, r7
849 
 
850 
	                   @ sendlcdc register map:
851 
	                   @ R0: Command to be sent
852 
	                   @ R8: LCD base address
853 
			   @ R9: Will be set to 0
854 
                           @ R14: Return address
855 
 
856 
sendlcdc:
857 
	ldr	r9, [r8,#0x1c]
858 
	ands	r9, r9, #0x10
859 
	bne	sendlcdc
860 
	str	r0, [r8,#0x04]
861 
	mov	pc, lr
862 
 
863 
	                   @ sendlcdd register map:
864 
	                   @ R0: Data to be sent
865 
	                   @ R8: LCD base address
866 
			   @ R9: Will be set to 0
867 
                           @ R14: Return address
868 
 
869 
sendlcdd:
870 
	ldr	r9, [r8,#0x1c]
871 
	ands	r9, r9, #0x10
872 
	bne	sendlcdd
873 
	str	r0, [r8,#0x40]
874 
	mov	pc, lr
875 
 
876 
	                   @ readlcd register map:
877 
	                   @ R0: Result data
878 
	                   @ R8: LCD base address
879 
                           @ R14: Return address
880 
 
881 
readlcd:
882 
	ldr	r0, [r8,#0x1c]
883 
	tst	r0, #2
884 
	beq	readlcd
885 
	str	r0, [r8,#0x10]
886 
readlcd_wait:
887 
	ldr	r0, [r8,#0x1c]
888 
	tst	r0, #0x1
889 
	beq	readlcd_wait
890 
	ldr	r0, [r8,#0x14]
891 
	mov	r0, r0,lsr#1
892 
	mov	pc, lr
893 
 
894 
lcddone:
895 
	ldr	r0, _stubend
896 
	adr	r1, _stubend + 4
897 
	mov	r2, #0x08000000
898 
	add	r0, r1, r0
899 
movepayloadloop:
900 
	cmp	r0, r1
901 
	ldrhi	r3, [r1], #4
902 
	strhi	r3, [r2], #4
903 
	bhi	movepayloadloop
904 
	mcr	p15, 0, r9,c7,c14,0 @ clean & invalidate data cache
905 
	mcr	p15, 0, r9,c7,c10,4 @ drain write buffer
906 
	mcr	p15, 0, r9,c7,c5    @ invalidate instruction cache
907 
	mov	pc, #0x08000000
908 
 
909 
values1:
910 
	block0_constpool
911 
	block1_constpool
912 
	gpio_initdata
913 
	pmu_batch_1
914 
	pmu_batch_2
915 
	pmu_batch_3
916 
	pmu_batch_4
917 
	pmu_batch_5
918 
	block6_constpool
919 
	lcd_sequences
920 
	.align	2
921 
 
922 
_stubend: